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參數(shù)資料
| 型號： | AD9398KSTZ-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE 100MHZ HDMI 100LQFP |
| 標準包裝： | 90 |
| 應(yīng)用： | 視頻 |
| 接口： | HDMI |
| 電源電壓： | 3.15 V ~ 3.47 V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 配用： | AD9398/PCBZ-ND - BOARD EVALUATION FOR AD9398 |
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AD9398
Rev. 0 | Page 28 of 44
0x2E—Bit[7] Ctrl Enable
When set, this bit allows Ctrl [3:0] signals decoded from the
DVI to be output on the I2S data pins. 0 = I2S signals on I2S
lines. 1 = Ctrl[3:0] output on I2S lines. The power-up default
setting is 0.
0x2E—Bits[6:5] I2S Output Mode
These bits select between four options for the I2S output: I2S,
right-justified, left-justified, or raw IEC60958 mode. The
power-up default setting is 00.
Table 15. I2S Output Select
I2S Output Mode
Result
00
I2S mode
01
Right-justified
10
Left-justified
11
Raw IEC60958 mode
0x2E—Bits[4:0] I2S Bit Width
These bits set the I2S bit width for right-justified mode. The
power-up default setting is 24 bits.
0x2F—Bit[6] TMDS Sync Detect
This read-only bit indicates the presence of a TMDS DE.
0 = no TMDS DE present. 1 = TMDS DE detected.
0x2F—Bit[5] TMDS Active
This read-only bit indicates the presence of a TMDS clock.
0 = no TMDS clock present. 1 = TMDS clock detected.
0x2F—Bit[4] AV Mute
This read-only bit indicates the presence of AV mute based on
general control packets. 0 = AV not muted. 1 = AV muted.
0x2F—Bit[3] HDCP Keys Read
This read-only bit reports if the HDCP keys were read
successfully. 0 = failure to read HDCP keys. 1 = HDCP keys
read.
0x2F—Bits[2:0] HDMI Quality
These read-only bits indicate a level of HDMI quality based on
the DE (display enable) edges. A larger number indicates a
higher quality.
0x30—Bit[6] HDMI Content Encrypted
This read-only bit is high when HDCP decryption is in use
(content is protected). The signal goes low when HDCP is not
being used. Customers can use this bit to determine whether to
allow copying of the content. The bit should be sampled at
regular intervals because it can change on a frame-by-frame
basis. 0 = HDCP not in use. 1 = HDCP decryption in use.
0x30—Bit[5] DVI HSYNC Polarity
This read-only bit indicates the polarity of the DVI HSYNC.
0 = DVI HSYNC polarity is low active. 1 = DVI HSYNC
polarity is high active.
0x30—Bit[4] DVI VSYNC Polarity
This read-only bit indicates the polarity of the DVI VSYNC.
0 = DVI VSYNC polarity is low active. 1 = DVI VSYNC polarity
is high active.
0x30—Bits[3:0] HDMI Pixel Repetition
These read-only bits indicate the pixel repetition on DVI.
0 = 1×, 1 = 2×, 2 = 3×, up to a maximum repetition of
10× (0x9).
Table 16.
Select
Repetition Multiplier
0000
1×
0001
2×
0010
3×
0011
4×
0100
5×
0101
6×
0110
7×
0111
8×
1000
9×
1001
10×
MACROVISION
0x31—Bits[7:4] Macrovision Pulse Max
These bits set the pseudo sync pulse width maximum for
Macrovision detection in pixel clocks. This is functional for
13.5 MHz SDTV or 27 MHz progressive scan. Power-up
default is 9.
0x31—Bits[3:0] Macrovision Pulse Min
These bits set the pseudo sync pulse width maximum for
Macrovision detection in pixel clocks. This is functional for
13.5 MHz SDTV or 27 MHz progressive scan. Power-up
default is 6.
0x32—Bit[7] Macrovision Oversample Enable
Tells the Macrovision detection engine whether oversampling
is used. This accommodates 27 MHz sampling for SDTV and
54 MHz sampling for progressive scan and is used as a
correction factor for clock counts. Power-up default is 0.
0x32—Bit[6] Macrovision PAL Enable
Tells the Macrovision detection engine to enter PAL mode when
set to 1. Default is 0 for NTSC mode.
0x32—Bit[5:0] Macrovision Line Count Start
Set the start line for Macrovision detection. Along with
Register 0x33, Bits [5:0], they define the region where MV
pulses are expected to occur. The power-up default is Line 13.
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