參數(shù)資料
型號(hào)： AD9398KSTZ-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 30/44頁(yè)
文件大?。?/td> 0K
描述： IC INTERFACE 100MHZ HDMI 100LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： 視頻
接口： HDMI
電源電壓： 3.15 V ~ 3.47 V
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 管件
安裝類型： 表面貼裝
配用： AD9398/PCBZ-ND - BOARD EVALUATION FOR AD9398
AD9398
Rev. 0 | Page 36 of 44
2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface control interface is provided in the
AD9398. Up to two AD9398 devices can be connected to the
2-wire serial interface, with a unique address for each device.
The 2-wire serial interface comprises a clock (SCL) and a
bidirectional data (SDA) pin. The analog flat panel interface
acts as a slave for receiving and transmitting data over the serial
interface. When the serial interface is not active, the logic levels
on SCL and SDA are pulled high by external pull-up resistors.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA must
change only when SCL is low. If SDA changes state while SCL is
high, the serial interface interprets that action as a start or stop
sequence.
There are six components to serial bus operation:
Start signal
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
Acknowledge (Ack)
When the serial interface is inactive (SCL and SDA are high),
communications are initiated by sending a start signal. The start
signal is a high-to-low transition on SDA while SCL is high.
This signal alerts all slave devices that a data transfer sequence
is coming.
The first 8 bits of data transferred after a start signal comprise a
7-bit slave address (the first 7 bits) and a single R/W bit (the 8th
bit). The R/W bit indicates the direction of data transfer, read
from (1) or write to (0) the slave device. If the transmitted slave
address matches the address of the device (set by the state of the
SA0 input pin as shown in Table 37), the AD9398 acknowledges
by bringing SDA low on the 9th SCL pulse. If the addresses do
not match, the AD9398 does not acknowledge.
Table 37. Serial Port Addresses
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
A6 (MSB)
A5
A4
A3
A2
A1
A0
1
0
1
0
DATA TRANSFER VIA SERIAL INTERFACE
For each byte of data read or written, the MSB is the first bit of
the sequence.
If the AD9398 does not acknowledge the master device during a
write sequence, the SDA remains high so the master can gener-
ate a stop signal. If the master device does not acknowledge the
AD9398 during a read sequence, the AD9398 interprets this as
the end of data. The SDA remains high, so the master can
generate a stop signal.
To write data to specific control registers of the AD9398, the 8-
bit address of the control register of interest must be written
after the slave address has been established. This control register
address is the base address for subsequent write operations. The
base address auto-increments by 1 for each byte of data written
after the data byte intended for the base address. If more bytes
are transferred than there are available addresses, the address
does not increment and remains at its maximum value. Any
base address higher than the maximum value does not produce
an acknowledge signal.
Data are read from the control registers of the AD9398 in a
similar manner. Reading requires two data transfer operations:
The base address must be written with the R/W bit of the
slave address byte low to set up a sequential read
operation.
Reading (the R/W bit of the slave address byte high) begins
at the previously established base address. The address of
the read register auto-increments after each byte is
transferred.
To terminate a read/write sequence to the AD9398, a stop signal
must be sent. A stop signal comprises a low-to-high transition
of SDA while SCL is high.
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first genera-
ting a stop signal to terminate the current communication. This
is used to change the mode of communication (read, write)
between the slave and master without releasing the serial
interface lines.
SDA
SCL
tBUFF
tSTAH
tDHO
tDSU
tDAL
tDAH
tSTASU
tSTOSU
05678-008
Figure 9. Serial Port Read/Write Timing
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