參數(shù)資料
型號: AD9398KSTZ-100
廠商: Analog Devices Inc
文件頁數(shù): 41/44頁
文件大?。?/td> 0K
描述: IC INTERFACE 100MHZ HDMI 100LQFP
標(biāo)準(zhǔn)包裝: 90
應(yīng)用: 視頻
接口: HDMI
電源電壓: 3.15 V ~ 3.47 V
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 管件
安裝類型: 表面貼裝
配用: AD9398/PCBZ-ND - BOARD EVALUATION FOR AD9398
AD9398
Rev. 0 | Page 6 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
05678-002
V
DD
RE
D
0
RE
D
1
RE
D
2
RE
D
3
RE
D
4
RE
D
5
RE
D
6
RE
D
7
GND
V
DD
DATACK
DE
HS
OUT
NC
VSOU
T
O/E
FIELD
SD
A
SC
L
P
W
RDN
V
D
NC
GND
NC
V
D
26
I2
S1
27
I2
S0
28
S/PD
IF
29
GND
30
DV
DD
31
GND
32
DV
DD
33
V
D
34
Rx
0–
35
R
x0+
36
GND
37
Rx
1–
38
R
x1+
39
GND
2
GREEN 7
3
GREEN 6
4
GREEN 5
7
GREEN 2
6
GREEN 3
5
GREEN 4
1
GND
8
GREEN 1
9
GREEN 0
10
VDD
12
BLUE 7
13
BLUE 6
14
BLUE 5
15
BLUE 4
16
BLUE 3
17
BLUE 2
18
BLUE 1
19
BLUE 0
20
MCLKIN
21
MCLKOUT
22
SCLK
23
LRCLK
24
I2S3
25
I2S2
11
GND
74
NC
GND
73
NC
72
VD
69
GND
70
NC
71
NC
75
68
NC
67
VD
66
NC
64
GND
63
GND
62
GND
61
GND
60
GND
59
PVDD
58
GND
57
FILT
56
PVDD
55
GND
54
PVDD
53
GND
52
MDA
51
MCL
65
GND
40
Rx
2–
41
R
x2+
42
GND
43
Rx
C+
44
Rx
C–
45
V
D
46
RTE
R
M
47
GND
48
DV
DD
49
DDCS
CL
50
DDCS
DA
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PIN 1
AD9398
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Figure 2. Pin Configuration
Table 5. Complete Pinout List
Pin Type
Pin No.
Mnemonic
Function
Value
INPUTS
81
PWRDN
Power-Down Control
3.3 V CMOS
DIGITAL VIDEO DATA INPUTS
35
Rx0+
Digital Input Channel 0 True
TMDS
34
Rx0
Digital Input Channel 0 Complement
TMDS
38
Rx1+
Digital Input Channel 1 True
TMDS
37
Rx1
Digital Input Channel 1 Complement
TMDS
41
Rx2+
Digital Input Channel 2 True
TMDS
40
Rx2
Digital Input Channel 2 Complement
TMDS
DIGITAL VIDEO CLOCK INPUTS
43
RxC+
Digital Data Clock True
TMDS
44
RxC
Digital Data Clock Complement
TMDS
OUTPUTS
92 to 99
RED [7:0]
Outputs of Red Converter, Bit 7 is MSB
VDD
2 to 9
GREEN [7:0]
Outputs of Green Converter, Bit 7 is MSB
VDD
12 to 19
BLUE [7:0]
Outputs of Blue Converter, Bit 7 is MSB
VDD
89
DATACK
Data Output Clock
VDD
87
HSOUT
HSYNC Output Clock (Phase-Aligned with DATACK)
VDD
85
VSOUT
VSYNC Output Clock (Phase-Aligned with DATACK)
VDD
84
FIELD
Odd/Even Field Output
VDD
REFERENCES
57
FILT
Connection for External Filter Components For audio
PLL
PVDD
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