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| 型號： | AD9430BSVZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 170MSPS 3.3V100TQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.43mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
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AD9430
Rev. E | Page 27 of 44
A1
VREF
1k
Ω
SENSE
200
Ω
0.1
μF
DISABLE
A1
VDD
K
FULL
SCALE
+
1V
3.3V
EXTERNAL 1.23V
REFERENCE
+
S5 = 0 —> K = 1.24
S5 = 1 —> K = 0.62
02607-054
LVDS OUTPUTS
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin S2. LVDS outputs are
available when S2 = VDD and a 3.74 kΩ RSET resistor is placed
at Pin 7 (LVDSBIAS) to ground. The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential
termination resistor placed at the LVDS receiver inputs results
in a nominal 350 mV swing at the receiver. LVDS mode
facilitates interfacing with LVDS receivers in custom ASICs and
FPGAs that have LVDS capability for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
as close to the receiver as possible. It is recommended to keep
the trace length three to four inches maximum and to keep
differential output trace lengths as equal as possible.
Figure 54. Using an External Reference
NOISE POWER RATIO TESTING (NPR)
NPR is a test that is commonly used to characterize the return
path of cable systems where the signals are typically QAM
signals with a noise-like frequency spectrum. NPR performance
of the AD9430 was characterized in the lab yielding an effective
NPR = 56.9 dB at an analog input of 19 MHz. This agrees with
a theoretical maximum NPR of 57.1 dB for an 11-bit ADC at
13.6 dB backoff. The rms noise power of the signal inside the
notch is compared with the rms noise level outside the notch
using an FFT. Sufficiently long record lengths to guarantee a
sufficient number of samples inside the notch are a
requirement, as well as a high order band-stop filter that
provides the required notch depth for testing.
CLOCK OUTPUTS (DCO+, DCO–)
The input ENCODE is divided by two (in CMOS mode) and
available off chip at DCO+ and DCO–. These clocks can
facilitate latching off chip, providing a low skew clocking
solution (see Figure 2). The on-chip clock buffers should not
drive more than 5 pF of capacitance to limit switching transient
effects on performance. Note that the output clocks are CMOS
levels when CMOS mode is selected (S2 = 0) and are LVDS
levels when in LVDS mode (S2 = VDD), requiring a 100 Ω
differential termination at receiver in LVDS mode. The output
clock in LVDS mode switches at the ENCODE rate.
VOLTAGE REFERENCE
A stable and accurate 1.23 V voltage reference is built into the
AD9430 (VREF). The analog input full-scale range is linearly
proportional to the voltage at VREF. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. No appreciable degradation in
performance occurs when VREF is adjusted ±5%. A 0.1 μF
capacitor to ground is recommended at the VREF pin in
internal and external reference applications. Float the SENSE
pin for internal reference operation.
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