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| 型號(hào)： | AD9513/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 13/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9513 |
| 設(shè)計(jì)資源： | AD9513/14/15 Eval Brd Schematics AD9513/14/15 Gerber Files AD9513 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘分配 |
| 已用 IC / 零件： | AD9513 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9513BCPZ-ND - IC CLOCK DIST 3OUT PLL 32LFCSP AD9513BCPZ-REEL7-ND - IC CLOCK DIST 3OUT PLL 32LFCSP |
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AD9513
Rev. 0 | Page 20 of 28
Table 16. OUT0 Divide or OUT2 Divide
S9
S10
OUT0
Divide (Duty Cycle1)
S2 ≠ 2/3
OUT2
Divide (Duty Cycle1)
S2 = 2/3
0
1
7 (43%)
1/3
0
2 (50%)
11 (45%)
2/3
0
3 (33%)
13 (46%)
1
0
4 (50%)
14 (50%)
0
1/3
5 (40%)
17 (47%)
1/3
6 (50%)
19 (47%)
2/3
1/3
8 (50%)
20 (50%)
1
1/3
9 (44%)
21 (48%)
0
2/3
10 (50%)
22 (50%)
1/3
2/3
12 (50%)
23 (48%)
2/3
15 (47%)
25 (48%)
1
2/3
16 (50%)
26 (50%)
0
1
18 (50%)
27 (48%)
1/3
1
24 (50%)
28 (50%)
2/3
1
30 (50%)
29 (48%)
1
32 (50%)
31 (48%)
1 Duty cycle is the clock signal high time divided by the total period.
DIVIDER PHASE OFFSET
The phase offset of OUT1 and OUT2 can be selected (see Table 13
to Table 15). This allows the relative phase of the outputs to be set.
After a SYNC operation (see the Synchronization section), the
phase offset word of each divider determines the number of
input clock (CLK) cycles to wait before initiating a clock output
edge. By giving each divider a different phase offset, output-to-
output delays can be set in increments of the fast clock period, tCLK.
Figure 24 shows four cases, each with the divider set to divide = 4.
By incrementing the phase offset from 0 to 3, the output is
offset from the initial edge by a multiple of tCLK.
01
4
123
5
9
67
8
10
14
11 12 13
5
tCLK
CLOCK INPUT
CLK
DIVIDER OUTPUT
DIV = 4
PHASE = 0
PHASE = 1
PHASE = 2
PHASE = 3
tCLK
2 × tCLK
3 × tCLK
05
59
5-
02
4
Figure 24. Phase Offset—Divider Set for Divide = 4, Phase Set from 0 to 2
For example:
CLK = 491.52 MHz
tCLK = 1/491.52 = 2.0345 ns
For Divide = 4:
Phase Offset 0 = 0 ns
Phase Offset 1 = 2.0345 ns
Phase Offset 2 = 4.069 ns
Phase Offset 3 = 6.104 ns
The outputs can also be described as:
Phase Offset 0 = 0°
Phase Offset 1 = 90°
Phase Offset 2 = 180°
Phase Offset 3 = 270°
Setting the phase offset to Phase = 4 results in the same relative
phase as Phase = 0° or 360°.
The resolution of the phase offset is set by the fast clock period
(tCLK) at CLK. The maximum unique phase offset is less than the
divide ratio, up to a phase offset of 15.
Phase offsets can be related to degrees by calculating the phase
step for a particular divide ratio:
Phase Step = 360°/Divide Ratio
Using some of the same examples:
Divide = 4
Phase Step = 360°/4 = 90°
Unique Phase Offsets in Degrees Are Phase = 0°, 90°,
180°, 270°
Divide = 9
Phase Step = 360°/9 = 40°
Unique Phase Offsets in Degrees Are Phase = 0°, 40°, 80°,
120°, 160°, 200°, 240°, 280°, 320°
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9514 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514/PCB | 制造商:Analog Devices 功能描述:CLOCK DISTRIBUTION - Bulk |
| AD9514/PCBZ | 功能描述:BOARD EVAL CLOCK 3CH AD9514 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9514BCPZ | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9514BCPZ-REEL7 | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無(wú) 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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