- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16847 > AD9513/PCBZ (Analog Devices Inc)BOARD EVAL FOR AD9513 PDF資料下載
參數(shù)資料
| 型號： | AD9513/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9513 |
| 設(shè)計資源： | AD9513/14/15 Eval Brd Schematics AD9513/14/15 Gerber Files AD9513 Eval Brd BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘分配 |
| 已用 IC / 零件： | AD9513 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9513BCPZ-ND - IC CLOCK DIST 3OUT PLL 32LFCSP AD9513BCPZ-REEL7-ND - IC CLOCK DIST 3OUT PLL 32LFCSP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
AD9513
Rev. 0 | Page 24 of 28
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9513 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 32. The
far-end termination network should match the PCB trace
impedance and provide the desired switching point. The
reduced signal swing may still meet receiver input requirements
in some applications. This can be useful when driving long
trace lengths on less critical nets.
50
10
OUT1/OUT1B
SELECTED AS CMOS
VS
CMOS
3pF
100
05
595
-0
34
Figure 32. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9513 offers LVDS outputs that
are better suited for driving long traces where the inherent noise
immunity of differential signaling provides superior
performance for clocking converters.
SETUP PINS (S0 TO S10)
The setup pins that require a logic level of VS (internal self-
bias) should be tied together and bypassed to ground via a
capacitor.
The setup pins that require a logic level of VS should be tied
together, along with the VREF pin, and bypassed to ground via
a capacitor.
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits, the
implementation and construction of the PCB is as important
as the circuit design. Proper RF techniques must be used for
device selection, placement, and routing, as well as power
supply bypassing and grounding to ensure optimum
performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9516-1/PCBZ | BOARD EVALUATION FOR AD9516-1 |
| MAX876AESA+T | IC VREF SERIES PREC 10V 8-SOIC |
| 35PX22MEFC5X11 | CAP ALUM 22UF 35V 20% RADIAL |
| GCC07DRYS-S734 | CONN EDGECARD 14POS DIP .100 SLD |
| MAX6177BASA+ | IC VREF SERIES PREC 3.3V 8-SOIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9514 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514/PCB | 制造商:Analog Devices 功能描述:CLOCK DISTRIBUTION - Bulk |
| AD9514/PCBZ | 功能描述:BOARD EVAL CLOCK 3CH AD9514 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9514BCPZ | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9514BCPZ-REEL7 | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
發(fā)布緊急采購，3分鐘左右您將得到回復。