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參數(shù)資料
| 型號： | AD9513/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9513 |
| 設(shè)計資源： | AD9513/14/15 Eval Brd Schematics AD9513/14/15 Gerber Files AD9513 Eval Brd BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘分配 |
| 已用 IC / 零件： | AD9513 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9513BCPZ-ND - IC CLOCK DIST 3OUT PLL 32LFCSP AD9513BCPZ-REEL7-ND - IC CLOCK DIST 3OUT PLL 32LFCSP |
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AD9513
Rev. 0 | Page 21 of 28
DELAY BLOCK
OUT2 includes an analog delay element that gives variable time
delays (ΔT) in the clock signal passing through that output.
÷N
SELECT
LVDS
CMOS
T
MU
X
OUTPUT
DRIVER
FINE DELAY ADJUST
(16 STEPS)
FULL SCALE : 1.5ns, 5ns, 10ns
CLOCK INPUT
OUT1 ONLY
05595-
025
Figure 25. Analog Delay Block
The amount of delay that can be used is determined by the
output frequency. The amount of delay is limited to less than
one-half cycle of the clock period. For example, for a 10 MHz
clock, the delay can extend to the full 11.6 ns maximum. However,
for a 100 MHz clock, the maximum delay is less than 5 ns (or
half of the period).
The AD9513 allows for the selection of three full-scale delays,
1.8 ns, 6.0 ns, and 11.6 ns, set by delay full-scale (see Table 11).
Each of these full-scale delays can be scaled by 16 fine
adjustment values, which are set by the delay word (see Table 13).
The delay block adds some jitter to the output. This means that
the delay function should be used primarily for clocking digital
chips, such as FPGA, ASIC, DUC, and DDC, rather than for
supplying a sample clock for data converters. The jitter is higher
for longer full scales because the delay block uses a ramp and
trip points to create the variable delay. A longer ramp means
more noise has a chance of being introduced.
When the delay block is OFF (bypassed), it is also powered
down.
OUTPUTS
Each of the three AD9513 outputs can be selected either as
LVDS differential outputs or as pairs of CMOS single-ended
outputs. If selected as CMOS, the OUT is a noninverted, single-
ended output, and OUTB is an inverted, single-ended output.
OUTB
OUT
3.5mA
055
95-
027
Figure 26. LVDS Output Simplified Equivalent Circuit
05
595
-0
28
OUT1/
OUT1B
VS
Figure 27. CMOS Equivalent Output Circuit
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9514 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514/PCB | 制造商:Analog Devices 功能描述:CLOCK DISTRIBUTION - Bulk |
| AD9514/PCBZ | 功能描述:BOARD EVAL CLOCK 3CH AD9514 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| AD9514BCPZ | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9514BCPZ-REEL7 | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
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