參數(shù)資料
型號： AD9516-0/PCBZ
廠商： Analog Devices Inc
文件頁數(shù)： 23/80頁
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
設(shè)計資源： AD9516-0 BOM
AD9516 Eval Brd Schematic
AD9516 Gerber Files
標(biāo)準(zhǔn)包裝： 1
Data Sheet
AD9516-0
Rev. C | Page 3 of 80
REVISION HISTORY
2/13—Rev. B to Rev. C
Changes to Register 0x140 to Register 0x143 Default Values;
Table 52.............................................................................................56
Changes to Register 0x140 to Register 0x143 Default Values;
Table 57.............................................................................................71
Updated Outline Dimensions........................................................80
1/12—Rev. A to Rev. B
Changes to 0x232 Description Column, Table 62 ......................76
12/10—Rev. 0 to Rev. A
Changes to Features, Applications, and General Description.....1
Change to CPRSET Pin Resistor Parameter in Table 1................4
Change to P = 2 DM (2/3) Parameter in Table 2 ..........................5
Changes to Table 4 ............................................................................6
Changes to VCP Supply Parameter in Table 17.............................14
Change to θJA Value and Endnote in Table 19 .............................16
Added Exposed Paddle Notation to Figure 6; Changes to
Table 20.............................................................................................17
Added Figure 41; Renumbered Sequentially...............................24
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 22..........27
Changes to Table 24 ........................................................................29
Change to Configuration and Register Settings Section............31
Change to Phase Frequency Detector (PFD) Section ................32
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections .........33
Change to Figure 47; Added Figure 48.........................................33
Changes to Reference Switchover and VCXO/VCO
Feedback Divider N—P, A, B, R Sections .................................... 34
Changes to Table 28 ........................................................................ 35
Change to Holdover Section.......................................................... 37
Changes to VCO Calibration Section........................................... 39
Changes to Clock Distribution Section........................................ 40
Added Endnote to Table 34 ........................................................... 41
Changes to Channel Dividers—LVDS/CMOS Outputs
Section; Added Endnote to Table 39 ............................................ 43
Changes to Write Section............................................................... 50
Change to the Instruction Word (16 Bits) Section ..................... 51
Change to Figure 65........................................................................ 52
Added Thermal Performance Section.......................................... 54
Changes to Register Address 0x003 in Table 52.......................... 55
Changes to Table 53 ........................................................................ 59
Changes to Table 54 ........................................................................ 60
Changes to Table 55 ........................................................................ 66
Changes to Table 56 ........................................................................ 68
Changes to Table 57 ........................................................................ 71
Changes to Table 58 ........................................................................ 73
Changes to Table 59 ........................................................................ 74
Changes to Table 60 and Table 61................................................. 76
Added Frequency Planning Using the AD9516 Section............ 77
Changes to Figure 71 and Figure 73; Added Figure 72.............. 78
Changes to LVPECL Clock Distribution and LVDS Clock
Distribution Sections...................................................................... 78
Updated Outline Dimensions........................................................80
4/07—Revision 0: Initial Version
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參數(shù)描述
AD9516-1 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.5 GHz VCO
AD9516-1/PCBZ 功能描述:BOARD EVALUATION FOR AD9516-1 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9516-1BCPZ 功能描述:IC CLOCK GEN 2.5GHZ VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR
AD9516-1BCPZ-REEL7 功能描述:IC CLOCK GEN 2.5GHZ VCO 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
AD9516-1XCPZ 制造商:Analog Devices 功能描述:14-CHANNEL CLOCK GENERATOR WITH INTEGRATED 2.8 GHZ VCO - Bulk
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