參數(shù)資料
型號(hào)： AD9516-0/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 75/80頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
設(shè)計(jì)資源： AD9516-0 BOM
AD9516 Eval Brd Schematic
AD9516 Gerber Files
標(biāo)準(zhǔn)包裝： 1
Data Sheet
AD9516-0
Rev. C | Page 77 of 80
APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9516
The AD9516 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9516, keep in mind the following
guidelines.
The AD9516 has the following four frequency dividers: the
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
Within the AD9516 family, lower VCO frequencies generally
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the AD9516 family. If the desired
frequency plan can be achieved with a version of the AD9516
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter. However,
choosing a higher VCO frequency may result in more flexibility
in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current and, thus, allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool for
determining the optimal loop filter for a given application.
USING THE AD9516 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock.
Considering an ideal ADC of infinite resolution, where the step
size and quantization error can be ignored, the available SNR
can be expressed approximately by
π
×
=
J
At
f
dB
SNR
2
1
log
20
)
(
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 70 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
fA (MHz)
S
NR
(
d
B)
E
NO
B
10
1k
100
30
40
50
60
70
80
90
100
110
6
8
10
12
14
16
18
t
J = 100
f
S
200
f
S
400
f
S
1ps
2ps
10p
s
SNR = 20log
1
2πfAtJ
06419-
044
Figure 70. SNR and ENOB vs. Analog Input Frequency
See the AN-756 Application Note, Sampled Systems and the Effects
of Clock Phase Noise and Jitter; and the AN-501 Application Note,
Aperture Uncertainty and ADC System Performance, at
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
may result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9516 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
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