參數(shù)資料
型號(hào)： AD9516-0/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 73/80頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN 2.8GHZ VCO 64-LFCSP
設(shè)計(jì)資源： AD9516-0 BOM
AD9516 Eval Brd Schematic
AD9516 Gerber Files
標(biāo)準(zhǔn)包裝： 1
Data Sheet
AD9516-0
Rev. C | Page 75 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x19C
5
Bypass Divider 3.2
Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
4
Bypass Divider 3.1
Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass 3.1 divider logic (default).
1: bypasses 3.1 divider logic.
3
Divider 3 nosync
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2
Divider 3 force high
Force Divider 3 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
1
Start High Divider 3.2
Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
0
Start High Divider 3.1
Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
0x19D
0
Divider 3 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x19E
[7:4]
Low Cycles Divider 4.1
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 4.1
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x19F
[7:4]
Phase Offset Divider 4.2
Refer to LVDS/CMOS channel divider function description (default = 0x0).
[3:0]
Phase Offset Divider 4.1
Refer to LVDS/CMOS channel divider function description (default = 0x0).
0x1A0
[7:4]
Low Cycles Divider 4.2
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
High Cycles Divider 4.2
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x1A1
5
Bypass Divider 4.2
Bypasses (and powers down) 4.2 divider logic; route clock to 4.2 output.
0: does not bypass 4.2 divider logic (default).
1: bypasses 4.2 divider logic.
4
Bypass Divider 4.1
Bypasses (and powers down) 4.1 divider logic; route clock to 4.1 output.
0: does not bypass 4.1 divider logic (default).
1: bypasses 4.1 divider logic.
3
Divider 4 nosync
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
2
Divider 4 force high
Forces Divider 4 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
1
Start High Divider 4.2
Divider 4.2 starts high/low.
0: starts low (default).
1: starts high.
0
Start High Divider 4.1
Divider 4.1 starts high/low.
0: starts low (default).
1: starts high.
0x1A2
0
Divider 4 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
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