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| 型號： | AD9517-0A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9517-0A |
| 設計資源： | AD9517 Eval Brd Schematics AD9517 Gerber Files AD9517-0 BOM |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9517-0A |
| 主要屬性： | 2 輸入，12 輸出，2.8GHz VCO |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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AD9517-0
Data Sheet
Rev. E | Page 38 of 80
Holdover
The AD9517 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a state of high
impedance. This is useful when the PLL reference clock is lost.
Holdover mode allows the VCO to maintain a relatively
constant frequency even though there is no reference clock.
Without this function, the charge pump is placed into a
constant pump-up or pump-down state, resulting in a massive
VCO frequency shift. Because the charge pump is placed in a
high impedance state, any leakage that occurs at the charge
pump output or the VCO tuning node causes a drift of the VCO
frequency. This can be mitigated by using a loop filter that
contains a large capacitive component because this drift is
limited by the current leakage induced slew rate (ILEAK/C) of the
VCO control voltage. For most applications, the frequency
accuracy is sufficient for 3 sec to 5 sec.
Both a manual holdover, using the SYNC pin, and an automatic
holdover mode are provided. To use either function, the
holdover function must be enabled (Register 0x01D[0] and
Register 0x01D[2]).
Note that the VCO cannot be calibrated with the holdover
enabled because the holdover resets the N divider during
calibration, which prevents proper calibration. Disable holdover
before issuing a VCO calibration.
Manual Holdover Mode
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state as long as there is
no reference clock present.
The B-counter (in the N divider) is reset synchronously with
the charge pump leaving the high impedance state on the
reference path PFD event. This helps align the edges out of the
R and N dividers for faster settling of the PLL. Because the
prescaler is not reset, this feature works best when the B and R
numbers are close because this results in a smaller phase
difference for the loop to settle out.
When using this mode, set the channel dividers to ignore the
SYNC pin (at least after an initial SYNC event). If the dividers
are not set to ignore the SYNC pin, the distribution outputs turn
off each time SYNC is taken low to put the part into holdover.
Automatic/Internal Holdover Mode
When enabled, this function automatically puts the charge pump
into a high impedance state when the loop loses lock. The
assumption is that the only reason the loop loses lock is due to
the PLL losing the reference clock; therefore, the holdover function
puts the charge pump into a high impedance state to maintain
the VCO frequency as close as possible to the original frequency
before the reference clock disappears. See Figure 53 for a flowchart
of the automatic/internal holdover function operation.
NO
YES
PLL ENABLED
DLD == LOW
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
HIGH IMPEDANCE
CHARGE PUMP
REFERENCE
EDGE AT PFD?
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
DLD == HIGH
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x1D[3] = 1: USE LD PIN VOLTAGE
WITH HOLDOVER.
0x1D[3] = 0: IGNORE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF
THE DLD DELAY COUNTER) WITH THE
REFERENCE AND FEEDBACK CLOCKS
INSIDE THE LOCK WINDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEFORE THE HOLDOVER
FUNCTION CAN BE RETRIGGERED.
YES
06424-
069
Figure 53. Flowchart of Automatic/Internal Holdover Mode
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