參數(shù)資料
型號(hào)： AD9517-0A/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 70/80頁(yè)
文件大小： 0K
描述： BOARD EVALUATION FOR AD9517-0A
設(shè)計(jì)資源： AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-0 BOM
標(biāo)準(zhǔn)包裝： 1
主要目的： 計(jì)時(shí)，時(shí)鐘發(fā)生器
嵌入式： 否
已用 IC / 零件： AD9517-0A
主要屬性： 2 輸入，12 輸出，2.8GHz VCO
次要屬性： CMOS，LVPECL 和 LVDS 兼容
已供物品： 板
AD9517-0
Data Sheet
Rev. E | Page 72 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x143
[2:1]
OUT7 LVDS output current
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination ()
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
7
50
0
OUT7 power-down
Powers down output (LVDS/CMOS).
0: power on.
1: power off (default).
Table 58. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
Bits
Name
Description
0x190
[7:4]
Divider 0 low cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays
low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
Divider 0 high cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays
high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x191
7
Divider 0 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
6
Divider 0 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 0 force high
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
4
Divider 0 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 0 phase offset
Phase offset (default = 0x0).
0x192
1
Divider 0 direct to output
Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
0
Divider 0 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x196
[7:4]
Divider 1 low cycles
Number of clock cycles of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
Divider 1 high cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays
high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x197
7
Divider 1 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 1 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 1 force high
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
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