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參數(shù)資料
| 型號： | AD9517-0A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9517-0A |
| 設(shè)計資源： | AD9517 Eval Brd Schematics AD9517 Gerber Files AD9517-0 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9517-0A |
| 主要屬性： | 2 輸入，12 輸出，2.8GHz VCO |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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Data Sheet
AD9517-0
Rev. E | Page 39 of 80
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (Register 0x01D[3]), which causes the holdover
function to always sense LD as high. If DLD is used, it is possible
for the DLD signal to chatter some while the PLL is reacquiring
lock. The holdover function may retrigger, thereby preventing
the holdover mode from ever terminating. Use of the current
source lock detect mode is recommended to avoid this situation
(see the Current Source Digital Lock Detect section).
Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N
divider) is reset synchronously with the charge pump leaving
the high impedance state on the reference path PFD event. This
helps align the edges out of the R and N dividers for faster
settling of the PLL and to reduce frequency errors during
settling. Because the prescaler is not reset, this feature works
best when the B and R numbers are close because this results in
a smaller phase difference for the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if Register 0x01D[3] = 1) before it can
re-enter holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (Register 0x01C). If the loop loses
lock during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the internal/automatic holdover
function:
Register 0x018[6:5], lock detect counter. These bits change
the number of consecutive PFD cycles with edges inside the
lock detect window that are required for the DLD indicator
to indicate lock. This impacts the time required before the
LD pin can begin to charge as well as the delay from the end
of a holdover event until the holdover function can be
reengaged.
Register 0x018[3], disable digital lock detect. This bit must
be set to 0b to enable the DLD circuit. Internal/automatic
holdover does not operate correctly without the DLD function
enabled.
Register 0x01A[5:0], lock detect pin output select. Set these
bits to 000100b for the current source lock detect mode
if using the LD pin comparator. Load the LD pin with
a capacitor of an appropriate value.
Register 0x01D[3], enable LD pin comparator. 1 = enable,
0 = disable. When disabled, the holdover function always
senses the LD pin as high.
Register 0x01D[1], enable external holdover control.
Register 0x01D[0] and Register 0x01D[2], holdover
function enable. If holdover is disabled, both external
and internal/automatic holdover are disabled.
For example, to use automatic holdover with the following:
Automatic reference switchover, prefer REF1
Digital lock detect: five PFD cycles, high range window
Automatic holdover using the LD pin comparator
Set the following registers (in addition to the normal PLL registers):
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; lock detect window = high range.
Register 0x018[3] = 0b; DLD normal operation.
Register 0x01A[5:0] = 000100b; current source lock detect
mode.
Register 0x01B[7:0] = 0xF7; set REFMON pin to status of
REF1 (active low).
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[2]=1b; enable the holdover function.
Register 0x01D[1] = 0b; use internal/automatic holdover
mode.
Register 0x01D[0] = 1b; enable the holdover function.
(VCO calibration must be complete before this bit is enabled.)
Connect REFMON pin to REFSEL pin.
Frequency Status Monitors
The AD9517 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is shown
in Figure 54. The VCO status frequency monitor is also capable
of monitoring the CLK input if the CLK input is selected as the
input to the N divider.
The PLL reference frequency monitors have two threshold
frequencies: normal and extended (see Table 16). The reference
frequency monitor thresholds are selected in Register 0x01A.
The frequency monitor status can be found in Register 0x01F,
Bits[3:1].
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