- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9159 > AD9518-4ABCPZ (Analog Devices Inc)IC CLOCK GEN 6CH 1.8GHZ 48LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9518-4ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 6CH 1.8GHZ 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9518-4
Data Sheet
Rev. B | Page 28 of 64
In differential mode, the reference input pins are internally self-
biased so that they can be ac-coupled via capacitors. It is possible
to dc couple to these inputs. If the differential REFIN is driven
by a single-ended signal, the unused side (REFIN) should be
decoupled via a suitable capacitor to a quiet ground.
shows the equivalent circuit of REFIN.
VS
REF1
REF2
REFIN
150
10k
12k
10k
REFIN
85k
VS
85k
VS
06
43
3-
0
66
Figure 34. REFIN Equivalent Circuit
Reference Switchover
The AD9518 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9518 supports automatic and manual
PLL reference clock switching between REF1 (on Pin REFIN)
and REF2 (on Pin REFIN). This feature supports networking
and other applications that require smooth switching of redundant
references. When used in conjunction with the automatic holdover
function, the
can achieve a worst-case reference input
switchover with an output frequency disturbance as low as 10 ppm.
When using reference switchover, the single-ended reference
inputs should be dc-coupled CMOS levels and never be allowed
to go to high impedance. If these inputs are allowed to go to high
impedance, noise may cause the buffer to chatter, causing
a false detection of the presence of a reference.
Reference switchover can be performed manually or auto-
matically. Manual switchover is performed either through
Register 0x01C or by using the REF_SEL pin. Manual switchover
requires the presence of a clock on the reference input that is
being switched to, or that the deglitching feature be disabled
(Register 0x01C[7]). The reference switching logic fails if this
condition is not met, and the PLL does not reacquire.
Automatic revertive switchover relies on the REFMON pin to
indicate when REF1 disappears. By programming Register 0x01B =
0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed
to be high when REF1 is invalid, which commands the switch to
REF2. When REF1 is valid again, the REFMON pin goes low, and
the part again locks to REF1. It is also possible to use the STATUS
pin for this function, and REF2 can be used as the preferred
reference.
A switchover deglitch feature ensures that the PLL does not receive
rising edges that are far out of alignment with the newly selected
reference.
Automatic nonrevertive switching is not supported.
Reference Divider R
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16,383
by writing to Register 0x011 and Register 0x012. (Both R = 0 and
R = 1 give divide-by-1.) The output of the R divider goes to one
of the PFD inputs to be compared with the VCO frequency
divided by the N divider. The frequency applied to the PFD
must not exceed the maximum allowable frequency, which
depends on the antibacklash pulse setting (see Table 2).
The R counter has its own reset. The R counter can be reset
using the shared reset bit of the R, A, and B counters. It can
also be reset by a SYNC operation.
VCXO/VCO Feedback Divider N—P, A, B, R
The N divider is a combination of a prescaler (P) and two counters,
A and B. The total divider value is
N = (P × B) + A
where the value of P can be 2, 4, 8, 16, or 32.
Prescaler
The prescaler of the AD9518 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and a dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3,
4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 44, Register 0x016[2:0]. Not all
modes are available at all frequencies (see Table 2).
When operating the AD9518 in dual modulus mode (P//P + 1),
the equation used to relate input reference frequency to VCO
output frequency is
fVCO = (fREF/R) × (P × B + A) = fREF × N/R
However, when operating the prescaler in an FD mode of 1, 2,
or 3, the A counter is not used (A = 0) and the equation
simplifies to
fVCO = (fREF/R) × (P × B) = fREF × N/R
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,
in which case the previous equation also applies.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SM843256KA | IC SYNTHESIZER LVPECL 24TSSOP |
| V110A36H300BG3 | CONVERTER MOD DC/DC 36V 300W |
| VI-B4W-MV | CONVERTER MOD DC/DC 5.5V 150W |
| V110A36H300BG2 | CONVERTER MOD DC/DC 36V 300W |
| VE-B2Z-MW-F2 | CONVERTER MOD DC/DC 2V 40W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9518-4ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 1.8GHZ 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9518-4A-PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9518-4BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9518-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9520 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。