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參數(shù)資料
| 型號： | AD9518-4ABCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 52/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 6CH 1.8GHZ 48LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 托盤 |
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AD9518-4
Data Sheet
Rev. B | Page 56 of 64
Table 46. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
Bits
Name
Description
0x190
[7:4]
Divider 0 low cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
[3:0]
Divider 0 high cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
0x191
7
Divider 0 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
6
Divider 0 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 0 force high
Forces divider output to high. This requires that the Divider 0 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 0 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
4
Divider 0 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 0 phase offset
Phase offset (default = 0x0).
0x192
1
Divider 0 direct to output
Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
0
Divider 0 DCCOFF
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
0x193
[7:4]
Divider 1 low cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0xB).
[3:0]
Divider 1 high cycles
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0xB).
0x194
7
Divider 1 bypass
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
6
Divider 1 nosync
No sync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
5
Divider 1 force high
Forces divider output to high. This requires that the Divider 1 nosync bit (Bit 6) also be set.
This bit has no effect if the Divider 1 bypass bit (Bit 7) is set.
0: divider output forced to low (default).
1: divider output forced to high.
4
Divider 1 start high
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
[3:0]
Divider 1 phase offset
Phase offset (default = 0x0).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9518-4ABCPZ-RL7 | 功能描述:IC CLOCK GEN 6CH 1.8GHZ 48LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 時鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9518-4A-PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9518-4BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9518-4BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9520 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers |
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