參數(shù)資料
型號: AD9548BCPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 3/112頁
文件大?。?/td> 0K
描述: IC CLOCK GEN/SYNCHRONIZR 88LFCSP
產(chǎn)品變化通告: AD9548 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝: 400
類型: 時鐘/頻率發(fā)生器,同步器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 750kHz
電源電壓: 1.71 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 88-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 88-LFCSP-VQ(12x12)
包裝: 帶卷 (TR)
AD9548
Data Sheet
Rev. E | Page 100 of 112
Table 138. IRQ Monitor for Reference Inputs
Address
Bits
Bit Name
Description
0x0D06
[7]
Ref AA new profile
Indicates that Ref AA has switched to a new profile
[6]
Ref AA validated
Indicates that Ref AA has been validated
[5]
Ref AA fault cleared
Indicates that Ref AA has been cleared of a previous fault
[4]
Ref AA fault
Indicates that Ref AA has been faulted
[3]
Ref A new profile
Indicates that Ref A has switched to a new profile
[2]
Ref A validated
Indicates that Ref A has been validated
[1]
Ref A fault cleared
Indicates that Ref A has been cleared of a previous fault
[0]
Ref A fault
Indicates that Ref A has been faulted
0x0D07
[7]
Ref BB new profile
Indicates that Ref BB has switched to a new profile
[6]
Ref BB validated
Indicates that Ref BB has been validated
[5]
Ref BB fault cleared
Indicates that Ref BB has been cleared of a previous fault
[4]
Ref BB fault
Indicates that Ref BB has been faulted
[3]
Ref B new profile
Indicates that Ref B has switched to a new profile
[2]
Ref B validated
Indicates that Ref B has been validated
[1]
Ref B fault cleared
Indicates that Ref B has been cleared of a previous fault
[0]
Ref B fault
Indicates that Ref B has been faulted
0x0D08
[7]
Ref CC new profile
Indicates that Ref CC has switched to a new profile
[6]
Ref CC validated
Indicates that Ref CC has been validated
[5]
Ref CC fault cleared
Indicates that Ref CC has been cleared of a previous fault
[4]
Ref CC fault
Indicates that Ref CC has been faulted
[3]
Ref C new profile
Indicates that Ref C has switched to a new profile
[2]
Ref C validated
Indicates that Ref C has been validated
[1]
Ref C fault cleared
Indicates that Ref C has been cleared of a previous fault
[0]
Ref C fault
Indicates that Ref C has been faulted
0x0D09
[7]
Ref DD new profile
Indicates that Ref DD has switched to a new profile
[6]
Ref DD validated
Indicates that Ref DD has been validated
[5]
Ref DD fault cleared
Indicates that Ref DD has been cleared of a previous fault
[4]
Ref DD fault
Indicates that Ref DD has been faulted
[3]
Ref D new profile
Indicates that Ref D has switched to a new profile
[2]
Ref D validated
Indicates that Ref D has been validated
[1]
Ref D fault cleared
Indicates that Ref D has been cleared of a previous fault
[0]
Ref D fault
Indicates that Ref D has been faulted
Table 139. DPLL Status
Address
Bits
Bit Name
Description
0x0D0A
[7]
Offset slew limiting
The current closed-loop phase offset is rate limited.
[6]
Phase build-out
A phase build-out transition was made to the currently active reference.
[5]
Freq lock
The DPLL has achieved frequency lock.
[4]
Phase lock
The DPLL has achieved phase lock.
[3]
Loop switching
The DPLL is in the process of a reference switchover.
[2]
Holdover
The DPLL is in holdover mode.
[1]
Active
The DPLL is active (that is, operating in a closed-loop condition)
[0]
Free running
The DPLL is free running (that is, operating in an open-loop condition)
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