參數(shù)資料
型號: AD9572ACPZPEC-R7
廠商: Analog Devices Inc
文件頁數(shù): 3/20頁
文件大小: 0K
描述: IC PLL CLOCK GEN 25MHZ 40LFCSP
標(biāo)準(zhǔn)包裝: 750
類型: 時鐘發(fā)生器,扇出配送,多路復(fù)用器
PLL:
輸入: 晶體
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:7
差分 - 輸入:輸出: 無/是
頻率 - 最大: 156.25MHz
除法器/乘法器: 是/無
電源電壓: 2.97 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 40-WFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-WQ(6x6)
包裝: 帶卷 (TR)
AD9572
Rev. B | Page 11 of 20
Pin No.
Mnemonic
Description
33
VS
Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers.
35
VS
Power Supply Connection for the FC VCO.
37
FORCE_LOW
Forces the 33.33 MHz output into a low state.
38
N/A
Short to Pin 36.
39
VS
Power Supply Connection for the FC PLL.
40
VS
Power Supply Connection for Miscellaneous Logic.
1 The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to
ground (GND).
07
49
8-
0
24
50
50
CD
VS
CD
VS
CD
VS
CD
VS
RT = 100
0.22F
CD = 100nF||10nF
CD
VS
CD
VS
CD
RT = 100
50
50
RT = 100
50
50
CD
VS
CD
VS
25MHz
CX = 22pF
50
TO CMOS
INPUT
CD
VS
CD
VS
CD
VS
CD
VS
RT = 100
50
RT = 100
50
TO CMOS
INPUT
AD9572
106M
100M/125M
VS
33M
FREQSEL
106M
106
M
VS
GN
D
GND
NC
VS
25M
VS
XO
REFCLK
REFSEL
GND
BY
P
AS
S
1
T
EST
F
O
RCE
_L
O
W
VS
TE
S
T
TE
S
T
VS
156M
100M
/1
25M
B
Y
P
A
SS2
106
M
100M/125M
100M
/125M
156M
0.22F
Figure 7. Typical Application Schematic, LVDS Format Outputs, 1 × 25 MHz, 1 × 156.25 MHz, 2 × 125 MHz, and 2 × 106.25 MHz
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AD9572ACPZPEC-RL 功能描述:IC PLL CLOCK GEN 25MHZ 40LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器,PLL,頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML,PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤,16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?(3x3) 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND
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