參數(shù)資料
型號(hào)： AD9634BCPZRL7-170
廠商： Analog Devices Inc
文件頁數(shù)： 14/32頁
文件大小： 0K
描述： IC ADC 12BIT SRL 170MSPS 32LFCSP
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
采樣率（每秒）： 170M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 340mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-WQ（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 單端，1 個(gè)差分
AD9634
Rev. 0 | Page 21 of 32
AD8375
AD9634
1H
1nF
VPOS
VCM
15pF
68nH
2.5k║2pF
301
165
5.1pF
3.9pF
180nH
1000pF
1000pF 180nH
220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1H CHOKE INDUCTORS (0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz.
099
96-
0
47
Figure 50. Differential Input Configuration Using the AD8375
An alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone is to use an amplifier
with variable gain. The AD8375 digital variable gain amplifier
(DVGA) provides good performance for driving the AD9634.
Figure 50 shows an example of the AD8375 driving the AD9634
through a band-pass antialiasing filter.
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9634.
The full-scale input range can be adjusted by varying the reference
voltage via SPI. The input span of the ADC tracks reference
voltage changes linearly.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9634 sample clock inputs,
CLK+ and CLK, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins by
means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 51) and require no
external bias. If the inputs are floated, the CLK pin is pulled low
to prevent spurious clocking.
AVDD
CLK+
4pF
CLK–
0.9V
09
99
6-
0
48
Figure 51. Equivalent Clock Input Circuit
Clock Input Options
The AD9634 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless
of the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section.
Figure 52 and Figure 53 show two preferable methods for clocking
the AD9634 (at clock rates of up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using an RF balun or RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 625 MHz, and the RF transformer is
recommended for clock frequencies from 10 MHz to 200 MHz.
The back-to-back Schottky diodes across the secondary windings
of the transformer limit clock excursions into the AD9634 to
approximately 0.8 V p-p differential. This limit helps prevent the
large voltage swings of the clock from feeding through to other
portions of the AD9634, while preserving the fast rise and fall times
of the signal, which are critical for low jitter performance.
390pF
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
09
996-
05
6
Figure 52. Transformer Coupled Differential Clock (Up to 200 MHz)
390pF
CLOCK
INPUT
1nF
25
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
0
999
6-
0
57
Figure 53. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input pins
clock drivers offer excellent jitter performance.
100
0.1F
240
PECL DRIVER
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx,
ADCLKxxx
ADC
09
996
-0
51
Figure 54. Differential PECL Sample Clock (Up to 625 MHz)
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