- 您現在的位置：買賣IC網 > PDF目錄1988 > AD9634BCPZRL7-170 (Analog Devices Inc)IC ADC 12BIT SRL 170MSPS 32LFCSP PDF資料下載
參數資料
| 型號： | AD9634BCPZRL7-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT SRL 170MSPS 32LFCSP |
| 標準包裝： | 1,500 |
| 位數： | 12 |
| 采樣率（每秒）： | 170M |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 340mW |
| 電壓電源： | 模擬和數字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 32-LFCSP-WQ（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數目和類型： | 2 單端，1 個差分 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD9634
Rev. 0 | Page 23 of 32
POWER DISSIPATION AND STANDBY MODE
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. To put the part into standby
mode, set the internal power-down mode bits (Bits[1:0]) in the
power modes register (Address 0x08) to 10. See the Memory
Map section and AN-877 Application Note, Interfacing to High
Speed ADCs via SPI for additional details.
As shown in Figure 57, the power dissipated by the AD9634 is
proportional to its sample rate. The data in Figure 57 was taken
using the same operating conditions as those used for the Typical
Performance Characteristics section.
0.4
0.3
0.2
0.1
0
0.25
0.20
0.15
0.10
0.05
0
40 55 70 85 100 115 130 145 160 175 190 205 220 235 250
TO
TA
L
P
O
W
E
R
(W
)
S
UP
P
LY
CURRE
NT
(
A)
ENCODE FREQUENCY (MSPS)
TOTAL POWER
IAVDD
IDRVDD
09
99
6-
05
3
DIGITAL OUTPUTS
The AD9634 output drivers can be configured for either ANSI
LVDS or reduced swing LVDS using a 1.8 V DRVDD supply.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD9634 has a flexible three-state ability for the digital output
pins. The three-state mode is enabled using the SPI interface.
The data outputs can be three-stated by using the output enable
bar bit (Bit 4) in Register 0x14. This OEB function is not intended
for rapid access to the data bus.
Figure 57. AD9634-250 Power and Current vs. Sample Rate
By setting the internal power-down mode bits (Bits[1:0]) in the
power modes register (Address 0x08) to 01, the AD9634 is placed
in power-down mode. In this state, the ADC typically dissipates
5 mW. During power-down, the output drivers are placed in a
high impedance state.
Timing
The AD9634 provides latched data with a pipeline delay of 10 input
sample clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to
normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
Minimize the length of the output data lines as well as the loads
placed on these lines to reduce transients within the AD9634.
These transients may degrade converter dynamic performance.
The lowest typical conversion rate of the AD9634 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD9634 also provides the data clock output (DCO) intended
for capturing the data in an external register. Figure 2 shows
timing diagram of the AD9634 output modes.
ADC OVERRANGE (OR)
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange condition is
determined at the output of the ADC pipeline and, therefore, is
subject to a latency of 10 ADC clock cycles. An overrange at the
input is indicated by this bit 10 clock cycles after it occurs.
Table 10. Output Data Format
Input (V)
VIN+ VIN, Input Span = 1.75 V p-p (V)
Offset Binary Output Mode
Twos Complement Mode (Default)
OR
VIN+ VIN
< 0.875
0000 0000 0000
1000 0000 0000
1
VIN+ VIN
= 0.875
0000 0000 0000
1000 0000 0000
0
VIN+ VIN
= 0
1000 0000 0000
0000 0000 0000
0
VIN+ VIN
= +0.875
1111 1111 1111
0111 1111 1111
0
VIN+ VIN
> +0.875
1111 1111 1111
0111 1111 1111
1
相關PDF資料 |
PDF描述 |
|---|---|
| AD9637BCPZRL7-80 | IC ADC 12BIT SRL 80MSPS 64LFCSP |
| AD9639BCPZ-170 | IC ADC 12B 170MSPS QUAD 72LFCSP |
| AD9640ABCPZ-125 | IC ADC 14BIT 125MSPS 64LFCSP |
| AD9641BCPZ-80 | IC ADC 14BIT SRL 80MSPS 32LFCSP |
| AD9644BCPZ-80 | IC ADC 14BIT 80MSPS 3V 48LFCSP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9634BCPZRL7-210 | 功能描述:模數轉換器 - ADC 12 Bit 210 Msps ADC RoHS:否 制造商:Analog Devices 通道數量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD9634BCPZRL7-250 | 功能描述:模數轉換器 - ADC 12 Bit 250 Msps ADC RoHS:否 制造商:Analog Devices 通道數量: 結構: 轉換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD9635-125EBZ | 功能描述:BOARD EVAL FOR AD9635-125 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數轉換器 (ADC) 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數量:1 位數:12 采樣率（每秒）:94.4k 數據接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| AD9635BCPZ-125 | 功能描述:IC ADC 12BIT SRL 125MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
| AD9635BCPZ-80 | 功能描述:IC ADC 12BIT SRL 80MSPS 32LFCSP RoHS:是 類別:集成電路 (IC) >> 數據采集 - 模數轉換器 系列:- 標準包裝:1 系列:- 位數:14 采樣率（每秒）:83k 數據接口:串行，并聯(lián) 轉換器數目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復。