參數(shù)資料
型號(hào)： AD9707-DPG2-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/44頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9707
標(biāo)準(zhǔn)包裝： 1
系列： *
AD9704/AD9705/AD9706/AD9707
Data Sheet
Rev. B | Page 30 of 44
THEORY OF OPERATION
Figure 71 shows a simplified block diagram of the AD9707. The
AD9704/AD9705/AD9706/AD9707 consist of a DAC, digital
control logic, and full-scale output current control. The DAC
contains a PMOS current source array capable of providing a
nominal full-scale current (IOUTFS) of 2 mA and a maximum of
5 mA. The array is divided into 31 equal currents that make up the
five most significant bits (MSBs). The next four bits, or middle
bits, consist of 15 equal current sources whose value is 1/16 of an
MSB current source. The remaining LSBs are binary weighted frac-
tions of the current sources of the middle bits. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances the AD9704/AD9705/AD9706/AD9707 dynamic
performance for multitone or low amplitude signals and helps
maintain the high output impedance of the DAC (that is,
>200 MΩ).
All of these current sources are switched to one of the two
output nodes (IOUTA or IOUTB) via PMOS differential current
switches. The switches are based on the architecture pioneered
in the AD9764 family, with further refinements made to reduce
distortion contributed by the switching transient. This switch
architecture also reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9704/AD9705/AD9706/
AD9707 have separate power supply inputs (AVDD and DVDD)
that can operate independently over a 1.7 V to 3.6 V range. The
digital section, capable of operating at a rate of up to 175 MSPS,
consists of edge-triggered latches and segment decoding logic
circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.0 V band gap
voltage reference, and a reference control amplifier.
The DAC full-scale output current is regulated by the reference
control amplifier and can be set from 1 mA to 5 mA via an external
resistor, RSET, connected to the full-scale adjust (FS ADJ) pin.
The external resistor, in combination with both the reference
control amplifier and voltage reference, VREFIO, sets the reference
current, IREF, which is replicated to the segmented current sources
with the proper scaling factor. The full-scale current, IOUTFS, is
32 × IREF.
The AD9704/AD9705/AD9706/AD9707 provide the option of
setting the output common mode to a value other than ACOM
via the output common mode (OTCM) pin. This facilitates
interfacing the output of the AD9704/AD9705/AD9706/AD9707
directly to components that require common-mode levels greater
than 0 V.
SERIAL PERIPHERAL INTERFACE
The AD9704/AD9705/AD9706/AD9707 serial port is a flexible,
synchronous serial communications port allowing easy interfacing
to many industry-standard microcontrollers and microprocessors.
The serial I/O is compatible with most synchronous transfer
formats, including the Motorola SPI and Intel SSR protocols.
The interface allows read/write access to all registers that configure
the AD9704/AD9705/AD9706/AD9707. Single or multiple byte
transfers are supported, as well as MSB first or LSB first transfer
formats. The serial interface port of the AD9704/AD9705/AD9706/
AD9707 is configured as a single pin I/O. SPI terminal voltages
are referenced to ACOM.
General Operation of the Serial Interface
There are two phases to a communication cycle with the AD9704/
AD9705/AD9706/AD9707. Phase 1 is the instruction cycle, which
is the writing of an instruction byte into the AD9704/AD9705/
AD9706/AD9707, coincident with the first eight SCLK rising
edges. The instruction byte provides the AD9704/AD9705/
AD9706/AD9707 serial port controller with information regarding
the data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the upcoming
data transfer is read or write, the number of bytes in the data
transfer, and the starting register address for the first byte of the
data transfer.
0.1F
LSB
SWITCHES
SEGMENTED
SWITCHES
LATCHES
CURRENT
SOURCE
ARRAY
DIGITAL INPUTS (DB13 TO DB0) SLEEP/CSB
CMODE/SCLK
MODE/SDIO
SPI
IOUTB
IOUTA
OTCM
REFIO
FS ADJ
CLKVDD
CLKCOM
CLK–
CLK+
ACOM
AVDD
DVDD
DCOM
1.0V REF
RSET
1.7V TO 3.6V
1.7V
TO
3.6V
1.7V TO
3.6V
PIN/SPI/RESET
AD9707
05
92
6
-10
3
Figure 71. Simplified Block Diagram
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