R/W N1N0A4 A3 A2 A1 A0 D7N
參數(shù)資料
型號(hào): AD9707-DPG2-EBZ
廠商: Analog Devices Inc
文件頁數(shù): 26/44頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9707
標(biāo)準(zhǔn)包裝: 1
系列: *
AD9704/AD9705/AD9706/AD9707
Data Sheet
Rev. B | Page 32 of 44
R/W N1N0A4 A3 A2 A1 A0 D7N D6N D5N
D00
D10
D20
D30
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
05
92
6-
-091
Figure 72. Serial Register Interface Timing, MSB First Write
R/W N1 N0A4A3
A2 A1 A0
D7
D6N D5N
D00
D10
D20
D30
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
0
592
6-
090
Figure 73. Serial Register Interface Timing, MSB First Read
A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20
D7N
D6N
D5N
D4N
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
05
92
6-
08
9
Figure 74. Serial Register Interface Timing, LSB First Write
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
SDO
A0 A1 A2 A3 A4 N0 N1 R/W
D10 D20
D7N
D6N
D5N
D4N
0
59
26-
088
D0
Figure 75. Serial Register Interface Timing, LSB First Read
INSTRUCTION BIT 6
INSTRUCTION BIT 7
CSB
SCLK
SDIO
tDS
tDH
tPWH
tPWL
tSCLK
05
92
6
-09
2
Figure 76. Timing Diagram for SPI Register Write
I1
I0
D7
D6
D5
tHLD
tSU
CSB
SCLK
SDIO
059
26-
09
3
Figure 77. Timing Diagram for SPI Register Read
SPI REGISTER MAP
Table 15.
Mnemonic
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI CTL
0x00
SDIODIR
DATADIR
SWRST
LNGINS
PDN
Sleep
CLKOFF
EXREF
Data
0x02
DATAFMT
DCLKPOL
DESKEW
CLKDIFF
CALCLK
Version
0x0D
VER[3]
VER[2]
VER[1]
VER[0]
CALMEM
0x0E
CALMEM[1]
CALMEM[0]
DIVSEL[2]
DIVSEL[1]
DIVSEL[0]
MEMRDWR
0x0F
CALSTAT
CALEN
SMEMWR
SMEMRD
UNCAL
MEMADDR
0x10
MEMADDR[5]
MEMADDR[4]
MEMADDR[3]
MEMADDR[2]
MEMADDR[1]
MEMADDR[0]
MEMDATA
0x11
MEMDATA[5]
MEMDATA[4]
MEMDATA[3]
MEMDATA[2]
MEMDATA[1]
MEMDATA[0]
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