參數(shù)資料
型號(hào)： AD9709-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/32頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9709
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
系列： TxDAC®
DAC 的數(shù)量： 2
位數(shù)： 8
采樣率（每秒）： 125M
數(shù)據(jù)接口： 并聯(lián)
設(shè)置時(shí)間： 35ns
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： AD9709
相關(guān)產(chǎn)品： AD9709ASTZRL-ND - IC DAC 8BIT DUAL 125MSPS 48LQFP
AD9709ASTZ-ND - IC DAC 8BIT DUAL 125MSPS 48-LQFP
AD9709
Rev. B | Page 12 of 32
THEORY OF OPERATION
5V
CLK1/IQCLK CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH
CHANNEL 2 LATCH
MODE
DVDD1/
DVDD2
MULTIPLEXING LOGIC
5V
GAINCTRL
DCOM1/
DCOM2
SLEEP
ACOM
DVDD1/DVDD2
DCOM1/DCOM2
AD9709
RSET1
2k
0.1F
RSET2
2k
CLK
DIVIDER
DAC1
LATCH
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
WRT1/
IQWRT
RETIMED CLOCK OUTPUT*
LECROY 9210
PULSE
GENERATOR
50
DIGITAL
DATA
TEKTRONIX
AWG2021
WITH OPTION 4
WRT2/
IQSEL
*AWG2021 CLOCK RETIMED SUCH THAT
DIGITAL DATA TRANSITIONS ON FALLING
EDGE OF 50% DUTY CYCLE CLOCK.
PORT 1
PORT 2
IOUTA1
IOUTB1
IOUTA2
IOUTB2
DAC2
LATCH
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
TO HP3589A
OR EQUIVALENT
SPECTRUM/
NETWORK
ANALYZER
Mini-Circuits
T1-1T
50
50
00
60
6-
0
04
Figure 21. Basic AC Characterization Test Setup for AD9709, Testing Port 1 in Dual Port Mode, Using Independent GAINCTRL Resistors on FSADJ1 and FSADJ2
0.1F
5V
CLK1/IQCLK
CLK2/IQRESET
AVDD
FSADJ1
REFIO
FSADJ2
1.2V REF
CHANNEL 1 LATCH
CHANNEL 2 LATCH
MODE
DVDD1/
DVDD2
MULTIPLEXING LOGIC
5V
GAINCTRL
DCOM1/
DCOM2
SLEEP
DIGITAL DATA INPUTS
AD9709
RSET1
2k
IREF1
RSET2
2k
IREF2
WRT1/
IQWRT
PORT 1
PORT 2
WRT2/
IQSEL
IOUTB2
IOUTA2
IOUTB1
IOUTA1
PMOS
CURRENT
SOURCE
ARRAY
PMOS
CURRENT
SOURCE
ARRAY
CLK
DIVIDER
DAC1
LATCH
DAC2
LATCH
SEGMENTED
SWITCHES FOR
DAC1
LSB
SWITCH
SEGMENTED
SWITCHES FOR
DAC2
LSB
SWITCH
VDIFF = VOUTA – VOUTB
VOUT1A
VOUT1B
VOUT2A
VOUT2B
RL1A
50
RL1B
50
RL2A
50
RL2B
50
ACOM
0
06
-0
22
Figure 22. Simplified Block Diagram
FUNCTIONAL DESCRIPTION
Figure 22 shows a simplified block diagram of the AD9709. The
AD9709 consists of two DACs, each one with its own independent
digital control logic and full-scale output current control. Each
DAC contains a PMOS current source array capable of providing
up to 20 mA of full-scale current (IOUTFS).
The array is divided into 31 equal currents that make up the five
most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16th of an
MSB current source. The remaining LSB is a binary weighted
fraction of the middle bit current sources. Implementing the
middle and lower bits with current sources instead of an R-2R
ladder enhances the dynamic performance for multitone or low
amplitude signals and helps maintain the high output impedance
of each DAC (that is, >100 kΩ).
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching of complementary drive signals to the inputs of the
differential current switches.
The analog and digital sections of the AD9709 have separate
power supply inputs (that is, AVDD and DVDD1/DVDD2) that
can operate independently over a 3.3 V to 5 V range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
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