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參數(shù)資料
| 型號： | AD9726-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9726 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 設(shè)計(jì)資源： | AD9726 Eval Brd Schematic AD9726 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 400M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9726 |
| 相關(guān)產(chǎn)品： | AD9726BSVZ-ND - IC DAC 16IT LVDS 400MSPS 80-TQFP AD9726BSVZRL-ND - IC DAC 16IT LVDS 400MSPS 80-TQFP |
AD9726
Rev. B | Page 15 of 24
SERIAL PORT INTERFACE
Table 8. SPI Register Map
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x00
SDIODIR
DATADIR
SWRESET
SLEEP
PWRDWN
EXTREF
0x02
DATAFMT
DATARATE
INVDCLKI
INVDCLKO
DISDCLKO
SYNCMAN
SYNCUPD
SYNCALRM
0x0E
CALMEM[1]
CALMEM[0]
CALCLK[2]
CALCLK[1]
CALCLK[0]
0x0F
SCALSTAT
SELFCAL
XFERSTAT
MEMXFER
SMEMWR
SMEMRD
FMEMRD
UNCAL
0x10
MEMADR[7]
MEMADR[6]
MEMADR[5]
MEMADR[4]
MEMADR[3]
MEMADR[2]
MEMADR[1]
MEMADR[0]
0x11
MEMDAT[5]
MEMDAT[4]
MEMDAT[3]
MEMDAT[2]
MEMDAT[1]
MEMDAT[0]
0x15
SYNCOUT[1]
SYNCOUT[0]
0x16
BYPASS
SYNCEXT
SYNCIN[1]
SYNCIN[0]
Table 9. SPI Register Bit Default and Descriptions Values
Addr
Name
Bits
I/O
Default
Description
0x00
SDIODIR
7
I
0
0: SDIO is input only (4-wire SPI mode), and SDO is used for output.
1: SDIO is input/output (3-wire SPI mode), and SDO is unused.
DATADIR
6
I
0
0: SPI serial data byte is MSB first format.
1: SPI serial data byte is LSB first format.
SWRESET
5
I
0
SLEEP
4
I
0
1: analog outputs temporarily disabled.
PWRDWN
3
I
0
1: full device power-down; all circuits disabled except SPI.
EXTREF
0
I
0
0x02
DATAFMT
7
I
0
0: input data-word is twos complement binary format.
1: input data-word is unsigned binary format.
DATARATE
6
I
0
0: DDR mode.
1: SDR mode.
INVDCLKI
5
I
0
1: inverts the polarity of the data clock input.
INVDCLKO
4
I
0
1: inverts the polarity of the data clock output.
DISDCLKO
3
I
0
1: disables the data clock output.
SYNCMAN
2
I
0
1: enables sync manual mode; disables automatic update.
SYNCUPD
1
I
0
1: forces manual sync update.
SYNCALRM
0
O
0
1: indicates that sync logic requires update.
0x0E
CALMEM
[5:4]
O
00
2-bit SMEM contents and calibration status indicator.
00: uncalibrated; SMEM contains default values (63).
01: self-calibrated; SMEM contains values from self-calibration.
10: factory-calibrated; SMEM values are transferred from FMEM.
11: user-calibrated; SMEM contains user-entered values.
CALCLK
[2:0]
I
000
3-bit self-calibration clock divider ratio. Affects time available for algorithm settling. Each
000: self-calibration clock is DAC clock/4096 (maximum self-calibration settling time for
highest linearity accuracy).
001,010,011: self-calibration clock is DAC clock/2048,1024,512.
100,101,110: self-calibration clock is DAC clock/256,128,64.
111: self-calibration clock is DAC clock/32 (minimum self-calibration settling time for
fastest algorithm completion).
0x0F
SCALSTAT
7
O
0
1: indicates completion of self-calibration cycle.
SELFCAL
6
I
0
XFERSTAT
5
O
0
1: indicates completion of memory transfer cycle.
MEMXFER
4
I
0
SMEMWR
3
I
0
1: enables static memory (SMEM) write operation.
SMEMRD
2
I
0
1: enable sstatic memory (SMEM) read operation.
FMEMRD
1
I
0
1: enables factory memory (FMEM) read operation.
UNCAL
0
I
0
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