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參數(shù)資料
| 型號(hào)： | AD9726-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9726 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 設(shè)計(jì)資源： | AD9726 Eval Brd Schematic AD9726 Eval Brd BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 400M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9726 |
| 相關(guān)產(chǎn)品： | AD9726BSVZ-ND - IC DAC 16IT LVDS 400MSPS 80-TQFP AD9726BSVZRL-ND - IC DAC 16IT LVDS 400MSPS 80-TQFP |
AD9726
Rev. B | Page 16 of 24
Addr
Name
Bits
I/O
Default
Description
0x10
MEMADR
[7:0]
I
00000000
8-bit memory address value for read/write operations.
0x11
MEMDAT
[5:0]
I/O
000000
6-bit memory data value for read/write operations.
0x15
SYNCOUT
[1:0]
O
00
2-bit output value indicates current sync quadrant.
0x16
BYPASS
6
I
0
1: bypasses data synchronization circuitry. Data is sampled using the DAC clock (CLK±)
SYNCEXT
5
I
0
1: enables sync external mode; disable auto quadrant select.
SYNCIN
[4:3]
I
00
2-bit input value is used to specify the sync quadrant.
1 SWRESET also resets itself. SMEM contents are unaffected by SWRESET; however, CALMEM reports an uncalibrated state.
2 EXTREF is optional because the internal reference circuit is designed to be overdriven by an external source.
3 The self-calibration clock is also used for the memory transfer cycle; therefore, the CALCLK value affects the MEMXFER process time.
4 Register Bits 3:0 must all be 0 to assert SELFCAL. The time required for the self-calibration cycle is ~100 ms at 100 MHz with CALCLK = 0.
5 Register Bits 3:0 must all be 0 to assert MEMXFER. The time required for the memory transfer cycle is ~15 ms at 100 MHz with CALCLK = 0.
6 The UNCAL bit remains asserted after the cycle completes (SMEM contents held at default values) until the bit is cleared by the user.
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