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參數(shù)資料
| 型號： | AD9734BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 40/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT 1.2GSPS 160-CSPBGA |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,500 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 550mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-LFBGA，CSPBGA |
| 供應商設備封裝： | 160-CSPBGA（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 1.2G |
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AD9734/AD9735/AD9736
Rev. A | Page 45 of 72
AD973x BIST PROCEDURE
1.
Set RESET pin = 1.
2.
Set input DATA = 0x0000 for signed (0x2000 for
unsigned).
3.
Enable DATACLK_IN if it is not already running.
4.
Run for at least 16 DATACLK_IN cycles.
5.
Set RESET pin = 0.
6.
Run for at least 16 DATACLK_IN cycles.
7.
Set RESET pin = 1.
8.
Run for at least 16 DATACLK_IN cycles.
9.
Set RESET pin = 0.
10.
Set desired operating mode (1× mode and signed data are
default values and expected for the supplied BIST vectors).
11.
Set CLEAR (Reg. 17, Bit 0), SYNC_EN (Reg. 17, Bit 1),
and LVDS_EN (Reg. 17, Bit 2) high.
12.
Wait 50 DATACLK_IN cycles to allow 0s to propagate
through and clear sync signatures.
13.
Set CLEAR low.
14.
Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
Reg. 18) for each of the four SEL (Reg. 17, Bits 7:6) values
and verify they are all 0x00.
LVDS Phase 1
a.
Reg. 17 set to 0x26 (SEL1 = 0, SEL0 = 0,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
LVDS Phase 2
a.
Reg. 17 set to 0x66 (SEL1= 0, SEL0 = 1,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
SYNC Phase 1
a.
Reg. 17 set to 0xA6 (SEL1= 1, SEL0 = 0,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
SYNC Phase 2
a.
Reg. 17 set to 0xE6 (SEL1= 1, SEL0 = 1,
SIG_READ = 1, LVDS_EN = 1, SYNC_EN = 1).
b.
Read Reg. 20, Reg. 19, Reg. 18, and Reg. 17.
15.
Clock the BIST vector into the AD973x.
16.
After the BIST vector is clocked into the part, hold DATA
= 0x0000 for signed (0x2000 for unsigned); otherwise, the
additional nonzero data changes the signature.
17.
Read all signature registers (Reg. 21, Reg. 20, Reg. 19, and
Reg. 18, as described in Step 14 ) for each of the four SEL
(Reg. 17, Bits 7:6) values, and verify that they match the
expected signatures shown in Table 25.
18.
Flush the BIST circuitry. This must be done once before
valid data can be read. Loop back to Step 11 and rerun the
test to obtain the correct result.
Each time BIST mode is entered, this flush needs to
be performed once. Multiple BIST runs can be performed
without reflushing, as long as the device remains in
BIST mode.
AD973x EXPECTED BIST SIGNATURES
The BIST vectors provided on the AD973x-EB CD are in signed
mode, so no programming is necessary for the part to pass the
BIST. The BIST vector is for 1×, no FIFO, and signed data.
For testing all 14 input bits, use the vector all_bits_unsnew.txt
and verify against the signatures in Table 25.
Table 25. Expected BIST Data Readback for All Bits
LVDS Phase 1
LVDS Phase 2
SYNC Phase 1
SYNC Phase 2
CF71487C
66DF5250
CF71487C
66DF5250
For individual bit tests, use the vectors named bitn.txt (where n
is the desired bit number being tested) and compare them
against the values in Table 26.
Table 26. Expected BIST Data Readback for Individual Bits
Vector
Bit
Number
LVDS Rise
Expected
LVDS Fall
Expected
bit0.txt
0
AABF0A00
2A400500
bit1.txt
1
2BBF0A00
6B400500
bit2.txt
2
29BE0A00
E9400500
bit3.txt
3
2DBC0A00
ED410500
bit4.txt
4
25B80A00
E5430500
bit5.txt
5
35B00A00
F5470500
bit6.txt
6
15A00A00
D54F0500
bit7.txt
7
55800A00
955F0500
bit8.txt
8
D5C00A00
157F0500
bit9.txt
9
D5410A00
153E0500
bit10.txt
10
D5430B00
15BC0500
bit11.txt
11
D5470900
15B80400
bit12.txt
12
D54F0D00
15B00600
bit13.txt
13
D55F0500
15A00200
Note the following for Table 26:
The term rise refers to Phase 1 and fall refers to Phase 2.
Byte order is Decimal Register Address 21, Address 20,
Address 19, and Address 18.
SYNC phase should always equal LVDS phase in 1× mode.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9734BBCZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS |
| AD9734-DPG2-EBZ | 功能描述:BOARD EVAL FOR AD9734 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉換器 (DAC) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9734-EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9735 DAC, 10-/12-/14BIT, 1200 MSPS DACS - Trays |
| AD9734-EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9735 DAC, 10-/12-/14BIT, 1200 MSPS DACS - Bulk |
| AD9735 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14/12/10-Bit, 1200 MSPS D/A Converters |
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