參數(shù)資料
型號: AD9735BBCRL
廠商: Analog Devices Inc
文件頁數(shù): 1/72頁
文件大?。?/td> 0K
描述: IC DAC 12BIT 1.2GSPS 160CSPBGA
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 1,500
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 550mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 160-LFBGA,CSPBGA
供應商設備封裝: 160-CSPBGA(12x12)
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 2 電流,單極
采樣率(每秒): 1.2G
10-/12-/14-Bit, 1200 MSPS DACS
AD9734/AD9735/AD9736
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
Pin-compatible family
Excellent dynamic performance
AD9736: SFDR = 82 dBc at fOUT = 30 MHz
AD9736: SFDR = 69 dBc at fOUT = 130 MHz
AD9736: IMD = 87 dBc at fOUT = 30 MHz
AD9736: IMD = 82 dBc at fOUT = 130 MHz
LVDS data interface with on-chip 100 Ω terminations
Built-in self test
LVDS sampling integrity
LVDS-to-DAC data transfer integrity
Low power: 380 mW (IFS = 20 mA; fOUT = 330 MHz)
1.8/3.3 V dual-supply operation
Adjustable analog output
8.66 mA to 31.66 mA (RL = 25 Ω to 50 Ω)
On-chip 1.2 V reference
160-lead chip scale ball grid array (CSP_BGA) package
APPLICATIONS
Broadband communications systems
Cellular infrastructure (digital predistortion)
Point-to-point wireless
CMTS/VOD
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9736, AD9735, and AD9734 are high performance, high
frequency DACs that provide sample rates of up to 1200 MSPS,
permitting multicarrier generation up to their Nyquist
frequency. The AD9736 is the 14-bit member of the family,
while the AD9735 and the AD9734 are the 12-bit and 10-bit
members, respectively. They include a serial peripheral interface
(SPI) port that provides for programming of many internal
parameters and enables readback of status registers.
A reduced-specification LVDS interface is utilized to achieve
the high sample rate. The output current can be programmed
over a range of 8.66 mA to 31.66 mA. The AD973x family is
manufactured on a 0.18 μm CMOS process and operates from
1.8 V and 3.3 V supplies for a total power consumption of
380 mW in bypass mode. It is supplied in a 160-lead chip scale
ball grid array for reduced package parasitics.
FUNCTIONAL BLOCK DIAGRAM
LVDS
RE
CE
IV
E
R
S
Y
NCHRONIZE
R
BAND GAP
DATACLK_IN+
DATACLK_IN–
DB[13:0]–
DB[13:0]+
SPI
14-, 12-,
10-BIT DAC
CORE
IOUTA
IOUTB
SDO
SDIO
SCLK
CSB
LVDS
DRIV
E
R
CONTROLLER
REFERENCE
CURRENT
DACCLK–
IRQ
DACCLK+
I120
VREF
RESET
DATACLK_OUT+
DATACLK_OUT–
S1 S2 S3
C1
C2
C3
C2
C1S1
S3
S2
C3
04862-001
CLOCK
DISTRIBUTION
Figure 1.
PRODUCT HIGHLIGHTS
1.
Low noise and intermodulation distortion (IMD) features
enable high quality synthesis of wideband signals at inter-
mediate frequencies up to 600 MHz.
2.
Double data rate (DDR) LVDS data receivers support the
maximum conversion rate of 1200 MSPS.
3.
Direct pin programmability of basic functions or SPI port
access offers complete control of all AD973x family
functions.
4.
Manufactured on a CMOS process, the AD973x family
uses a proprietary switching technique that enhances
dynamic performance.
5.
The current output(s) of the AD9736 family are easily con-
figured for single-ended or differential circuit topologies.
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