參數(shù)資料
型號(hào)： AD9735BBCRL
廠商： Analog Devices Inc
文件頁數(shù)： 50/72頁
文件大?。?/td> 0K
描述： IC DAC 12BIT 1.2GSPS 160CSPBGA
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 550mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 160-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 160-CSPBGA（12x12）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 2 電流，單極
采樣率（每秒）： 1.2G
AD9734/AD9735/AD9736
Rev. A | Page 54 of 72
INPUT DATA TIMING
The AD973x is intended to operate with the LVDS and sync
controllers running to compensate for timing drift due to
voltage and temperature variations. In this mode, the key to
correct data capture is to present valid data for a minimum
amount of time. The AD973x minimum valid data time is
measured by increasing the input data rate to the point of
failure. The nominal supply voltages are used and the
temperature is set to the worst case of 85°C. The input
data is verified via the BIST signature registers, because the
DAC output does not run as fast as the input data logic. The
following example explains how the minimum data valid
period is calculated for the typical performance case.
These factors must be considered in determining the minimum
valid data window at the receiver input:
Data rise and fall times: 100 ps (rise + fall)
Internal clock jitter: 10 ps
(DATACLK_OUT + DATACLK_IN)
Bit-to-bit skew: 50 ps
Bit-to-DATACLK_IN skew: 50 ps
Internal data sampling signal resolution: 80 ps
For nominal silicon, the BIST typically indicates failure at
2.15 GSPS or a DACCLK period of 465 ps. The valid data
window is calculated by subtracting all the other variables
from the total data period:
Minimum Data Valid Time = DACCLK Period Data Rise
Data Fall Jitter Bit-to-Bit Skew Bit-to-DATACLK_IN Skew
Data Sampling Signal Resolution
For the 400 mV p-p LVDS signal case:
Minimum Data Valid = 465 ps 100 ps 10 ps 50 ps
80 ps = 465 ps 240 ps = 225 ps
For correct data capture, the input data must be valid for 225 ps.
Slower edges, more jitter, or more skew require an increase in
the clock period to maintain the minimum data valid period.
Table 27 shows the typical minimum data valid period (tMDE) for
400 mV p-p differential and 250 mV p-p differential LVDS swings.
The ability of the AD973x to capture incoming data is
dependent on the speed of the silicon, which varies from lot to
lot. The typical (or average) silicon speed operates with data
that is valid for 225 ps at 85°C. Statistically, the worst extreme
for slow silicon may require up to a 344 ps valid data period, as
specified in Table 2.
Table 27. Typical Minimum Data Valid Times
Differential Input
Voltage
BIST
Max fCLK
Min Clock
Period
Typ Min Data
Valid at Receiver
400 mV
2.15 GHz
465 ps
225 ps
250 mV
2.00 GHz
500 ps
260 ps
At 1.2 GHz, the typical 400 mV p-p minimum data valid period
of 225 ps leaves 608 ps for external factors. Under the same
conditions, the worst expected minimum data valid period of
344 ps leaves 489 ps for external data uncertainty.
The 100 mV LVDS VOD threshold test is a dc test to verify that
the input logic state changes. It does not indicate the operating
speed. The ability of the receiver to recover the data depends on
the input signal overdrive. With a 250 mV input, there is a
150 mV overdrive, and with a 400 mV signal, there is a 300 mV
overdrive. The relationship between overdrive level and timing
is very nonlinear. Higher levels of overdrive result in smaller
minimum valid data windows.
For typical silicon, decreasing the LVDS swing from 400 mV p-p
to 250 mV p-p requires the minimum data valid period to
increase by 15%. This is illustrated in Figure 100.
225ps
400mV
260ps
250mV
04862-098
Figure 100. Typical Minimum Valid Data Time (tMDE) vs. LVDS Swing
The minimum valid data window changes with temperature,
voltage, and process. The maximum value presented in the
specification table was determined from a 6σ distribution in the
worst-case conditions.
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AD9735BBCZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS
AD9735BBCZRL 功能描述:IC DAC 12BIT 1.2GSPS 160-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
AD9735BBCZRL1 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS
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