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參數(shù)資料
| 型號(hào)： | AD9735BBCRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 36/72頁(yè) |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT 1.2GSPS 160CSPBGA |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 550mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 160-CSPBGA（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極 |
| 采樣率（每秒）： | 1.2G |
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AD9734/AD9735/AD9736
Rev. A | Page 41 of 72
To find the leading edge of the data cycle, increment the
measured setup delay until the check bit goes low. To find the
trailing edge, increment the measured hold delay (MHD) until
check goes low. Always set MHD = 0 when incrementing MSD
and vice versa.
The incremental units of SD, MSD, and MHD are in units of real
time, not fractions of a clock cycle. The nominal step size is 80 ps.
OPERATING THE LVDS CONTROLLER IN
MANUAL MODE VIA THE SPI PORT
The manual operation of the LVDS controller allows the user to
step through both the setup and hold delays to calculate the
optimal sampling delay (that is, the center of the data eye).
With SD<3:0> and MHD<3:0> set to 0, increment the setup time
delay (MSD<3:0>, Reg. 4, Bits 7:4) until the check bit (Reg. 5,
Bit 0) goes low and record this value. This locates the leading
DATACLK_IN (and data) transition, as shown in Figure 80.
With SD<3:0> and MSD<3:0> set to 0, increment the hold time
delay (MHD<3:0>, Reg. 4, Bits 3:0) until the check bit (Reg. 5,
Bit 0) goes low and record this value. This locates the trailing
DATACLK_IN (and DB<13:0>) transition, as shown in Figure
Once both DATACLK_IN edges are located, the sample delay
(SD<3:0>, Reg. 5, Bits 7:4) must be updated by
Sample Delay = (MHD MSD)/2
After updating SD<3:0>, verify that the sampling signal is in the
middle of the valid data window by adjusting both MHD and
MSD with the new sample delay until the check bit goes low.
The new MHD and MSD values should be equal to or within
one unit delay if SD<3:0> was set correctly.
MHD and MSD may not be equal to or within one unit delay if
the external clock jitter and noise exceeds the internal delay
resolution. Differences of 2, 3, or more are possible and can
require more filtering to provide stable operation.
The sample delay calibration should be performed prior to
enabling surveillance mode or auto mode.
SETUP TIME (
tS)
SAMPLE DELAY
MSD<3:0> = 0 1 2 3 4 5
CSS SAMPLE DCS
CHECK = 1
SD<3:0>
DB<13:0>
DATACLK_IN
CSS WITH
MHD<3:0> = 0
DSC DELAYED
BY MSD<3:0>
04862-
078
Figure 80. Setup Delay Measurement
SETUP TIME (
tS)
HOLD TIME (
tH)
SAMPLE DELAY
CSS SAMPLE DCS
CHECK = 1 1 1 1 1 0
CHECK = 1
SD<3:0>
0
4862-
079
MSD<3:0> = 0 1 2 3 4 5
DB<13:0>
DATACLK_IN
CSS WITH
MHD<3:0> = 0
DSC DELAYED
BY MSD<3:0> = 0
Figure 81. Hold Delay Measurement
OPERATING THE LVDS CONTROLLER IN
SURVEILLANCE AND AUTO MODE
In surveillance mode, the controller searches for the edges of
the data eye in the same manner as in the manual mode of
operation and triggers an interrupt if the clock sampling signal
(CSS) has moved more than the threshold value set by
LTRH<1:0> (Reg. 6, Bits 1:0).
There is an internal filter that averages the setup and hold time
measurements to filter out noise and glitches on the clock lines.
Average Value = (MHD – MSD)/2
New Average = Average Value + (Δ Average/2 ^ LFLT<3:0>)
If an accumulating error in the average value causes it to exceed
the threshold value (LTHR<1:0>), an interrupt is issued.
The maximum allowable value for LFLT<3:0> is 12. If
LFLT<3:0> is too small, clock jitter and noise can cause erratic
behavior. In most cases, LFLT can be set to the maximum value.
In surveillance mode, the ideal sampling point should first be
found using manual mode and then applied to the sample delay
registers. Set the threshold and filter values depending on how
far the CSS signal is allowed to drift before an interrupt occurs.
Then, set the surveillance bit high (Reg. 6, Bit 7) and monitor
the interrupt signal either via the SPI port (Reg. 1, Bit 7) or the
IRQ pin.
In auto mode, follow the same steps to set up the sample delay,
threshold, and filter length. To run the controller in auto mode,
both the LAUTO (Reg. 6, Bit 6) and LSURV (Reg. 6, Bit 7) bits
need to be set to 1. In auto mode, the LVDS interrupt should be
set low (Reg. 1, Bit 3) to allow the sample delay to be automati-
cally updated if the threshold value is exceeded.
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| AD9735BBCZ | 功能描述:IC DAC 12BIT 1.2GSPS 160-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9735BBCZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS |
| AD9735BBCZRL | 功能描述:IC DAC 12BIT 1.2GSPS 160-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9735BBCZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 1200 MSPS DACS |
| AD9735-DPG2-EBZ | 功能描述:BOARD EVAL FOR AD9735 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時(shí)間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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