f
參數(shù)資料
型號(hào): AD9744ARZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 28/32頁(yè)
文件大小: 0K
描述: IC DAC 14BIT 210MSPS 28-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 27
系列: TxDAC®
設(shè)置時(shí)間: 11ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 模擬和數(shù)字
功率耗散(最大): 145mW
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 28-SOIC W
包裝: 管件
輸出數(shù)目和類(lèi)型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 210M
產(chǎn)品目錄頁(yè)面: 785 (CN2011-ZH PDF)
配用: AD9744ACP-PCBZ-ND - BOARD EVAL FOR AD9744ACP
Data Sheet
AD9744
Rev. C | Page 5 of 32
Parameter
Min
Typ
Max
Unit
Multitone Power Ratio (8 Tones at 400 kHz Spacing)
fCLOCK = 78 MSPS; fOUT = 15.0 MHz to 18.2 MHz
0 dBFS Output
66
dBc
6 dBFS Output
68
dBc
12 dBFS Output
62
dBc
18 dBFS Output
61
dBc
1
Measured single-ended into 50 Ω load.
2
Output noise is measured with a full-scale output set to 20 mA with no conversion activity. It is a measure of the thermal noise only.
3
Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone.
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS1
Logic 1 Voltage
2.1
3
V
Logic 0 Voltage
0
0.9
V
Logic 1 Current
10
+10
A
Logic 0 Current
10
+10
A
Input Capacitance
5
pF
Input Setup Time (tS)
2.0
ns
Input Hold Time (tH)
1.5
ns
Latch Pulse Width (tLPW)
1.5
ns
CLK INPUTS2
Input Voltage Range
0
3
V
Common-Mode Voltage
0.75
1.5
2.25
V
Differential Voltage
0.5
1.5
V
1
Includes CLOCK pin on SOIC/TSSOP packages and CLK+ pin on LFCSP package in single-ended clock input mode.
2
Applicable to CLK+ and CLK– inputs when configured for differential or PECL clock input mode.
Figure 2. Timing Diagram
0.1%
tS
tH
tPD
DB0–DB13
CLOCK
IOUTA
OR
IOUTB
02913-002
tLPW
tST
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