參數(shù)資料
| 型號： | AD9744ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 210MSPS 28-SOIC |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 27 |
| 系列： | TxDAC® |
| 設置時間： | 11ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 145mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 210M |
| 產品目錄頁面： | 785 (CN2011-ZH PDF) |
| 配用： | AD9744ACP-PCBZ-ND - BOARD EVAL FOR AD9744ACP |
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Data Sheet
AD9744
Rev. C | Page 15 of 32
for the AD9744 are measured with IOUTA maintained at a
virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of 1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the AD9744.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9744 digital section consists of 14 input bit channels
and a clock input. The 14-bit parallel data inputs follow
standard positive binary coding, where DB13 is the most
significant bit (MSB) and DB0 is the least significant bit (LSB).
IOUTA produces a full-scale output current when all data bits
are at Logic 1. IOUTB produces a complementary output with
the full-scale current split between the two outputs as a
function of the input code.
Figure 28. Equivalent Digital Input
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold
times can also be varied within the clock cycle as long as the
specified minimum times are met, although the location of
these transition edges may affect digital feedthrough and
distortion performance. Best performance is typically achieved
when the input data transitions on the falling edge of a 50%
duty cycle clock.
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock quality,
and jitter is a key concern. Any noise or jitter in the clock will
translate directly into the DAC output. Optimal performance
will be achieved if the CLOCK input has a sharp rising edge,
since the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes.
The mode selection is controlled by the CMODE input, as
summarized in Table 7. Connecting CMODE to CLKCOM
selects the single-ended clock input. In this mode, the CLK+
input is driven with rail-to-rail swings and the CLK– input is
left floating. If CMODE is connected to CLKVDD, the differential
receiver mode is selected. In this mode, both inputs are high
impedance. The final mode is selected by floating CMODE. This
mode is also differential, but internal terminations for positive
emitter-coupled logic (PECL) are activated. There is no significant
performance difference among any of the three clock input modes.
Table 7. Clock Mode Selection
CMODE Pin
Clock Input Mode
CLKCOM
Single-Ended
CLKVDD
Differential
Float
PECL
The single-ended input mode operates in the same way as the
CLOCK input in the 28-lead packages, as previously described.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave since
the high gain bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 29. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
DVDD
DIGITAL
INPUT
02913-025
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9744ARZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 210 MSPS TxDAC㈢ D/A Converter |
| AD9744ARZRL | 功能描述:IC DAC 14BIT 210MSPS 28-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC® 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD9744ARZRL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 210 MSPS TxDAC㈢ D/A Converter |
| AD9744-EB | 制造商:Analog Devices 功能描述:AD9744 EVALUATION BOARD (AD9744-EB) - Bulk |
| AD9745 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters |
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