參數(shù)資料
型號： AD9744ARZ
廠商： Analog Devices Inc
文件頁數(shù)： 8/32頁
文件大?。?/td> 0K
描述： IC DAC 14BIT 210MSPS 28-SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 27
系列： TxDAC®
設(shè)置時間： 11ns
位數(shù)： 14
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 145mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 210M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
配用： AD9744ACP-PCBZ-ND - BOARD EVAL FOR AD9744ACP
AD9744
Data Sheet
Rev. C | Page 16 of 32
Figure 29. Clock Termination in PECL Mode
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship
between the position of the clock edges and the time at which
the input data changes. The AD9744 is rising edge triggered,
and so exhibits dynamic performance sensitivity when the data
transition is close to this edge. In general, the goal when applying
the AD9744 is to make the data transition close to the falling
clock edge. This becomes more important as the sample rate
increases. Figure 30 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement,
while at higher rates, more care must be taken.
Figure 30. SFDR vs. Clock Placement at fOUT = 20 MHz and 50 MHz
Sleep Mode Operation
The AD9744 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over
the specified supply range of 2.7 V to 3.6 V and temperature
range. This mode can be activated by applying a logic level 1 to
the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9744 remains enabled if this
input is left disconnected. The AD9744 takes less than 50 ns to
power down and approximately 5 s to power back up.
POWER DISSIPATION
The power dissipation, PD, of the AD9744 is dependent on
several factors that include:
The power supply voltages (AVDD, CLKVDD, and
DVDD)
The full-scale current output IOUTFS
The update rate fCLOCK
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog supply
current, IAVDD, and the digital supply current, IDVDD. IAVDD is
directly proportional to IOUTFS, as shown in Figure 31, and is
insensitive to fCLOCK. Conversely, IDVDD is dependent on both the
digital input waveform, fCLOCK, and digital supply DVDD. Figure 32
shows IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
Figure 31. IAVDD vs. IOUTFS
Figure 32. IDVDD vs. Ratio at DVDD = 3.3 V
CLK+
TO DAC CORE
CLK–
VTT = 1.3V NOM
50
50
AD9744
CLOCK
RECEIVER
02913-026
–3
–2
2
–1
0
1
65
75
ns
dB
3
55
45
35
60
70
50
40
50MHz SFDR
20MHz SFDR
50MHz SFDR
02913-027
IOUTFS (mA)
35
0
2
I AVDD
(mA)
30
25
20
15
10
4
6
8
10
12
14
16
18
20
02913-028
RATIO (fOUT/fCLOCK)
20
0.01
1
0.1
I DVDD
(mA)
14
16
18
12
10
8
6
4
2
0
165MSPS
210MSPS
65MSPS
02913-029
125MSPS
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參數(shù)描述
AD9744ARZ1 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 210 MSPS TxDAC㈢ D/A Converter
AD9744ARZRL 功能描述:IC DAC 14BIT 210MSPS 28-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:*
AD9744ARZRL1 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 210 MSPS TxDAC㈢ D/A Converter
AD9744-EB 制造商:Analog Devices 功能描述:AD9744 EVALUATION BOARD (AD9744-EB) - Bulk
AD9745 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters
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