參數(shù)資料
型號(hào): AD9751-EB
廠商: Analog Devices Inc
文件頁(yè)數(shù): 25/28頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9751
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC®
DAC 的數(shù)量: 1
位數(shù): 10
采樣率(每秒): 300M
數(shù)據(jù)接口: 并聯(lián)
設(shè)置時(shí)間: 11ns
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD9751
相關(guān)產(chǎn)品: AD9751ASTZRL-ND - IC DAC 10BIT 300MSPS 48LQFP
AD9751ASTZ-ND - IC DAC 10BIT 300MSPS 48-LQFP
REV. C
AD9751
–6–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Description
1
RESET
Internal Clock Divider Reset
2
CLK+
Differential Clock Input
3
CLK–
Differential Clock Input
4, 22
DCOM
Digital Common
5, 21
DVDD
Digital Supply Voltage
6PLLLOCK
Phase-Locked Loop Lock Indicator Output
7–16
P1B9–P1B0
Data Bits P1B9 to P1B0, Port 1
17–20, 33–36
RESERVED
23–32
P2B9–P2B0
Data Bits P2B9 to P2B0, Port 2
37, 38
DIV0, DIV1
Control Inputs for PLL and Input Port Selector Mode; see Tables I and II for details.
39
REFIO
Reference Input/Output
40
FSADJ
Full-Scale Current Output Adjust
41
AVDD
Analog Supply Voltage
42
IOUTB
Differential DAC Current Output
43
IOUTA
Differential DAC Current Output
44
ACOM
Analog Common
45
CLKCOM
Clock and Phase-Locked Loop Common
46
LPF
Phase-Locked Loop Filter
47
PLLVDD
Phase-Locked Loop Supply Voltage
48
CLKVDD
Clock Supply Voltage
PIN CONFIGURATION
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
AD9751
RESERVED
P2B0–LSB
P2B1
P2B2
P2B3
P2B4
P2B5
P2B6
P2B7
RESET
CLK+
CLK–
DCOM
DVDD
PLLLOCK
MSB–P1B9
P1B8
P1B7
P1B6
P1B5
P1B4
CLKVDD
PLLVDD
LPF
CLKCOM
ACOM
I OUTA
I OUTB
AVDD
FSADJ
REFIO
DIV1
DIV0
P1B3
P1B2
P1B1
LSB–P1B0
RESERVED
DVDD
DCOM
MSB–P2B9
P2B8
RESERVED = NO
USER CONNECTIONS
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