- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17063 > AD9751-EB (Analog Devices Inc)BOARD EVAL FOR AD9751 PDF資料下載
參數(shù)資料
| 型號： | AD9751-EB |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9751 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 300M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時間： | 11ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9751 |
| 相關(guān)產(chǎn)品： | AD9751ASTZRL-ND - IC DAC 10BIT 300MSPS 48LQFP AD9751ASTZ-ND - IC DAC 10BIT 300MSPS 48-LQFP |
第1頁第2頁第3頁當(dāng)前第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
REV. C
AD9751
–12–
The effects of phase noise on the AD9751’s SNR performance
become more noticeable at higher reconstructed output fre-
quencies and signal levels. Figure 8 compares the phase noise of
a full-scale sine wave at exactly fDATA/4 at different data rates
(thus carrier frequency) with the optimum DIV1, DIV0 setting.
FREQUENCY OFFSET (MHz)
0
–20
–110
5
1
0
NOISE
DENSITY
(dBm/Hz)
–10
–30
–40
–50
–60
–70
–80
–90
–100
234
PLL ON, fDATA = 150MSPS
PLL OFF, fDATA = 50MSPS
PLL ON, fDATA = 50MSPS
PLL ON, fDATA = 100MSPS
PLL ON, fDATA = 125MSPS
Figure 8. Phase Noise of PLL Clock Multiplier at
fOUT = fDATA/4 at Different fDATA Settings with DIV0/DIV1
Optimized, Using R&S FSEA30 Spectrum Analyzer,
RBW = 30 kHz
SNR is partly a function of the jitter generated by the clock
circuitry. As a result, any noise on PLLVDD or CLKVDD may
degrade the SNR at the output of the DAC. To minimize this
potential problem, PLLVDD and CLKVDD can be connected
to DVDD using an LC filter network similar to the one shown
in Figure 9.
100 F
ELECT.
10 F–22 F
TANT.
0.1 F
CER.
TTL/CMOS
LOGIC
CIRCUITS
3.3V
POWER SUPPLY
FERRITE
BEADS
CLKVDD
PLLVDD
CLKCOM
Figure 9. LC Network for Power Filtering
DAC TIMING WITH PLL ACTIVE
As described in Figure 7, in PLL ACTIVE mode, Port 1 and
Port 2 input latches are updated on the rising edge of CLK. On
the same rising edge, data previously present in the input Port 2
latch is written to the DAC output latch. The DAC output will
update after a short propagation delay (tPD).
Following the rising edge of CLK, at a time equal to half of its
period, the data in the Port 1 latch will be written to the DAC
output latch, again with a corresponding change in the DAC
output. Due to the internal PLL, the time at which the data in
the Port 1 and Port 2 input latches is written to the DAC latch
is independent of the duty cycle of CLK.
When using the PLL,
the external clock can be operated at any duty cycle that meets
the specified input pulsewidth.
On the next rising edge of CLK, the cycle begins again with the
two input port latches being updated and the DAC output latch
being updated with the current data in the Port 2 input latch.
PLL DISABLED MODE
When PLLVDD is grounded, the PLL is disabled. An external
clock must now drive the CLK inputs at the desired DAC output
update rate. The speed and timing of the data present at input
Ports 1 and 2 is now dependent on whether or not the AD9751
is interleaving the digital input data or only responding to data
on a single port. Figure 10 is a functional block diagram of the
AD9751 clock control circuitry with the PLL disabled.
PLLVDD
TO DAC
LATCH
PLLLOCK
CLOCK
LOGIC
( 1 OR
2)
DIFFERENTIAL
TO
SINGLE-ENDED
AMP
TO
INTERNAL
MUX
CLKIN+
CLKIN–
AD9751
RESET DIV0 DIV1
TO INPUT
LATCHES
Figure 10. Clock Circuitry with PLL Disabled
DIV0 and DIV1 no longer control the PLL, but are used to set
the control on the input mux for either interleaving or not
interleaving the input data. The different modes for states of
DIV0 and DIV1 are given in Table II.
Table II. Input Mode for DIV0,
DIV1 Levels with PLL Disabled
Input Mode
DIV1
DIV0
Interleaved (2
×)0
0
Noninterleaved
Port 1 Selected
0
1
Port 2 Selected
1
0
Invalid
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MLG1005S10NJ | INDUCTOR MULTILAYER 10NH 0402 |
| GCM10DCMT-S288 | CONN EDGECARD 20POS .156 EXTEND |
| UPB2E271MRD | CAP ALUM 270UF 250V 20% RADIAL |
| ECE-V1EA101P | CAP ALUM 100UF 25V 20% SMD |
| MLK1005S15NJ | INDUCTOR MULTILAYER 15NH 0402 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9752 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9752AR | 功能描述:IC DAC 12BIT 125MSPS 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9752ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT 125 MSPS+ TXDAC D/A CONVERTER - Tape and Reel |
| AD9752ARU | 功能描述:IC DAC 12BIT 125MSPS HP 28-TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。