參數(shù)資料
型號: AD9755-EB
廠商: Analog Devices Inc
文件頁數(shù): 15/28頁
文件大小: 0K
描述: BOARD EVAL FOR AD9755
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準包裝: 1
系列: TxDAC+®
DAC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 300M
數(shù)據(jù)接口: 并聯(lián)
設(shè)置時間: 11ns
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD9755
相關(guān)產(chǎn)品: AD9755ASTZRL-ND - IC DAC 14BIT 300MSPS 48-LQFP
AD9755ASTZ-ND - IC DAC 14BIT 300MSPS 48-LQFP
REV. B
AD9755
–22–
116
2B13
2
4
6
8
12
10
16
14
P2
P2B13
1
215
2B12
P2B12
2
314
2B11
P2B11
3
413
2B10
P2B10
4
512
2B09
P2B09
5
611
2B08
P2B08
6
710
2B07
P2B07
7
89
2B06
P2B06
8
9
10
RN8
VALUE
RN7
VALUE
P2
1
3
5
7
9
11
13
15
1
2
3
4
5
6
7
8
9
10
2B13
2B12
2B11
2B10
2B09
2B08
2B07
2B06
RN9
VALUE
116
1B13
2
4
6
8
12
10
16
14
P1
P1B13
1
215
1B12
P1B12
2
314
1B11
P1B11
3
413
1B10
P1B10
4
512
1B09
P1B09
5
611
1B08
P1B08
6
710
1B07
P1B07
7
89
1B06
P1B06
8
9
10
RN2
VALUE
RN1
VALUE
P1
11
13
15
1
3
5
7
9
116
1B05
18
20
22
24
28
26
32
30
P1
17
19
21
23
25
27
29
31
P1
P1B05
1
215
1B04
P1B04
2
314
1B03
P1B03
3
413
1B02
P1B02
4
512
1B01
P1B01
5
611
1B00
P1B00
6
710
1O17
OUT15
7
89
OUT16
8
9
10
RN5
VALUE
RN4
VALUE
36
34
40
38
P1
33
35
37
39
25 26 27 28 29 30 31 32 33 34 35 36
U1
AD9751/AD9753/AD9755
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
22
23
24
21
12 11 10 9
8
3
2
1
76
54
P2B12
MSB
P2B13
P2B11
P2B10
P2B09
P2B08
P2B07
P2B06
P2B05
P2B04
P2B03
P2B02
P2B01
P2B00 LSB
S
P
1
2
3
JP9
AVDD PLANE
1
2
3
JP8
AVDD_PLANE
DIV0
DIV1
AB
REFIO
FSADJ
C12
0.1 F
WHT
TP2
WHT
TP1
R1
1.91k
DVDD PLANE
P1B12
P1B11
P1B10
P1B09
P1B08
P1B07
P1B06
P1B05
P1B04
P1B03
P1B02
P1B01
P1B00 LSB
P1B13 MSB
CLKVDD
IA
IB
P
LPF
C11
1.0 F
R5
392
R10
OPT
4
6
1
2
3
T1
BL1
BL2
1
2
IOUT
J5
1
2
DGND: 3,4,5
J1
DVDD PLANE
CLK+
CLK–
RESET
1
2
3
JP5
RESET
A
B
R4
50
WHT
TP3
OUT16
EDGE
EXT
R3
50
C10
10pF
R2
50
C9
10pF
NOTE:
SHIELD AROUND
R5 AND C11 ARE
CONNECTED TO
PLLVDD PLANE
1
2
3
4
5
6
7
8
9
10
1B13
1B12
1B11
1B10
1B09
1B08
1B07
1B06
RN3
VALUE
1B05
1B04
1B03
1B02
1B01
1B00
1O16
RN6
VALUE
1
2
3
4
5
6
7
8
9
10
1O17
1O15
JP10
BLK
TP4
BLK
TP5
BLK
TP6
116
2B05
18
20
22
24
28
26
32
30
P2
17
19
21
23
25
27
29
31
P2
P2B05
1
215
2B04
P2B04
2
314
2B03
P2B03
3
413
2B02
P2B02
4
512
2B01
P2B01
5
611
2B00
P2B00
6
710
7
89
8
9
10
RN11
VALUE
RN10
VALUE
36
34
40
38
P2
33
35
37
39
P2OUT15
P2OUT16
2B05
2B04
2B03
2B02
2B01
2B00
RN12
VALUE
1
2
3
4
5
6
7
8
9
10
2OUT15
2OUT16
NOTES
1. ALL DIGITAL INPUTS FROM RN1–RN12
MUST BE OF EQUAL LENGTH.
2. ALL DECOUPLING CAPS TO BE LOCATED
AS CLOSE AS POSSIBLE TO DUT,
PREFERABLY UNDER DUT ON BOTTOM
SIGNAL LAYER.
3. CONNECT GNDS UNDER DUT USING
BOTTOM SIGNAL LAYER.
4. CREATE PLANE CAPACITOR WITH 0.007"
DIELECTRIC BETWEEN LAYERS 2 AND 3.
BLK
TP7
BLK
TP8
BLK
TP9
P
BLK
TP10
BLK
TP12
1O15
1O16
Figure 34. Evaluation Board Circuitry
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