DIGITAL SPECIFICATIONS (T MIN to T
參數(shù)資料
型號(hào): AD9755-EB
廠商: Analog Devices Inc
文件頁數(shù): 23/28頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9755
產(chǎn)品培訓(xùn)模塊: DAC Architectures
標(biāo)準(zhǔn)包裝: 1
系列: TxDAC+®
DAC 的數(shù)量: 1
位數(shù): 14
采樣率(每秒): 300M
數(shù)據(jù)接口: 并聯(lián)
設(shè)置時(shí)間: 11ns
DAC 型: 電流
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: AD9755
相關(guān)產(chǎn)品: AD9755ASTZRL-ND - IC DAC 14BIT 300MSPS 48-LQFP
AD9755ASTZ-ND - IC DAC 14BIT 300MSPS 48-LQFP
REV. B
AD9755
–4–
DIGITAL SPECIFICATIONS (T
MIN to TMAX, AVDD = DVDD = PLLVDD = CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
DIGITAL INPUTS
Logic 1
2.1
3
V
Logic 0
0
0.9
V
Logic 1 Current
–10
+10
A
Logic 0 Current
–10
+10
A
Input Capacitance
5
pF
Input Setup Time (tS), TA = 25
°C
1.0
0.5
ns
Input Hold Time (tH), TA = 25
°C
1.0
0.5
ns
Latch Pulsewidth (tLPW), TA = 25
°C
1.5
ns
Input Setup Time (tS, PLLVDD = 0 V), TA = 25
°C
–1.0
–1.5
ns
Input Hold Time (tH, PLLVDD = 0 V), TA = 25
°C
2.5
1.7
ns
CLK to PLLLOCK Delay (tD, PLLVDD = 0 V), TA = 25
°C
3.5
4.0
ns
Latch Pulsewidth (tLPW PLLVDD = 0 V), TA = 25
°C
1.5
ns
PLLOCK (VOH)
3.0
V
PLLOCK (VOL)
0.3
V
CLK INPUTS
Input Voltage Range
0
3
V
Common-Mode Voltage
0.75
1.5
2.25
V
Differential Voltage
0.5
1.5
V
Min CLK Frequency
*
6.25
MHz
*Min CLK Frequency only applies when using internal PLL. When PLL is disabled, there is no minimum CLK frequency.
Specifications subject to change without notice.
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