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參數(shù)資料
| 型號： | AD9762ARZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 125MSPS 28-SOIC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 27 |
| 系列： | TxDAC® |
| 設(shè)置時間： | 35ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 160mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 125M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
AD9762
–18–
REV. B
REFIO
FS ADJ
IOUTA
IOUTB
CLOCK
RSET
2k *
RCAL1
50
CLOCK
U1
I-CHANNEL
50 **
RLOAD
50 **
RLOAD
TO
NYQUIST
FILTER
AND MIXER
REFIO
FS ADJ
IOUTA
IOUTB
CLOCK
RSET
2k *
RCAL2
100
U2
Q-CHANNEL
50 **
RLOAD
50 **
RLOAD
TO
NYQUIST
FILTER
AND MIXER
0.1 F
REFLO
AVDD
* OHMTEK ORNA1001F
** OHMTEK TOMC1603-50F
Figure 57. Baseband QAM Implementation Using Two
AD9762s
It is also possible to generate a QAM signal completely in the
digital domain via a DSP or ASIC, in which case only a single
DAC of sufficient resolution and performance is required to
reconstruct the QAM signal. Also available from several vendors
are Digital ASICs which implement other digital modulation
schemes such as PSK and FSK. This digital implementation has
the benefit of generating perfectly matched I and Q components
in terms of gain and phase, which is essential in maintaining
optimum performance in a communication system. In this
implementation, the reconstruction DAC must be operating at a
sufficiently high clock rate to accommodate the highest specified
QAM carrier frequency. Figure 58 shows a block diagram of
such an implementation using the AD9762.
50
AD9762
LPF
50
TO
MIXER
STEL-1130
QAM
12
COS
12
SIN
12
I DATA
Q DATA
12
CARRIER
FREQUENCY
12
STEL-1177
NCO
CLOCK
Figure 58. Digital QAM Architecture
AD9762 EVALUATION BOARD
General Description
The AD9762-EB is an evaluation board for the AD9762 12-bit
D/A converter. Careful attention to layout and circuit design
combined with a prototyping area allow the user to easily and
effectively evaluate the AD9762 in any application where high
resolution, high speed conversion is required.
This board allows the user the flexibility to operate the AD9762
in various configurations. Possible output configurations include
transformer coupled, resistor terminated, inverting/noninverting
and differential amplifier outputs. The digital inputs are designed
to be driven directly from various word generators, with the
on-board option to add a resistor network for proper load
termination. Provisions are also made to operate the AD9762
with either the internal or external reference, or to exercise
the power-down feature.
Refer to the application note AN-420 “Using the AD9760/
AD9762/AD9764-EB Evaluation Board” for a thorough
description and operating instructions for the AD9762
evaluation board.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9762ARZRL | 功能描述:IC DAC 12BIT 125MSPS 28-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD9762-EB | 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
| AD9762-EBZ | 功能描述:BOARD EVAL FOR AD9762 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9763 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 125 MSPS Dual TxDAC+ D/A Converter |
| AD9763_11 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-/12-/14-Bit, 125 MSPS Dual TxDAC Digital-to-Analog Converters |
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