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參數(shù)資料
| 型號(hào)： | AD976BRRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/16頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 100KSPS 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)單端，雙極 |
| 配用： | EVAL-AD976CB-ND - BOARD EVAL FOR AD976 EVAL-AD976ACB-ND - BOARD EVAL FOR AD976A |
AD976/AD976A
–8–
REV. C
DATA
VALID
t
6
t
3
t
1
t
10
t
9
CONVERT
ACQUIRE
MODE
DATA
BUS
NOT
VALID
HI-Z
DATA
VALID
BUSY
R/
C
t
7
t
8
t
11
t
13
ACQUIRE
t
2
t
4
PREVIOUS
DATA VALID
t
5
PREVIOUS
DATA VALID
t
14
HI-Z
Figure 2. Conversion Timing with Outputs Enabled After Conversion (CS Tied Low)
MODE
BUSY
R/
C
DATA
BUS
CS
t
6
t
12
t
1
CONVERT
ACQUIRE
HI-Z
DATA VALID
t
7
ACQUIRE
t
9
t
12
t
12
t
12
t
1
t
3
t
4
t
14
HI-Z
Figure 3. Using CS to Control Conversion and Read Timing
CONVERSION CONTROL
The AD976/AD976A is controlled by two signals: R/C and CS,
as shown in Figures 2 and 3. To initiate a conversion and place
the sample/hold circuit into the hold state, both the R/C and CS
signals must be brought low for no less than 50 ns. Once the
conversion process begins, the BUSY signal will go Low until
the conversion is complete. At the end of a conversion, BUSY
will return High, and the resulting valid data will be available on
the data bus. On the first conversion after the AD976/AD976A
is powered up, the DATA output will be indeterminate.
The AD976/AD976A exhibits two modes of conversion. In the
mode demonstrated in Figure 2, conversion timing is controlled
by a negative-going R/C signal, at least 50 ns wide. In this mode
the CS pin is always tied low, and the only limit placed on how
long the R/C signal can remain low is the desired sampling rate.
Less than 83 ns after the initiation of a conversion, the BUSY
signal will be brought low and remain low until the conversion is
complete and the output shift registers have been updated with
the new Binary Twos Complement data.
Figure 3 demonstrates the AD976/AD976A conversion timing,
using CS to control both the conversion process and the reading
of output data. To operate in this mode, the R/C signal should
be brought low no less than 10 ns before the falling edge of a CS
pulse (50 ns wide) is applied to the ADC. Once these two pulses
are applied, BUSY will go low and remain low until a conver-
sion is complete. After a maximum of 4
s (AD976A only),
BUSY will again return high, and parallel data will be valid on
the ADC outputs. To achieve the maximum 100 kHz/200 kHz
throughput rate of the part, the negative going R/C and CS
control signals should be applied every 5
s (AD976A). It should
also be noted that although all R/C and CS commands will be
ignored once a conversion has begun, these inputs can be
asserted during a conversion; i.e., a read during conversion can
be performed. Voltage transients on these inputs could feed
through to the analog circuitry and affect conversion results.
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| AD976BRSRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel 28-Pin SSOP T/R |
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| AD976BRSZRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 16-bit Parallel 28-Pin SSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 16BIT PARALLEL 28SSOP - Tape and Reel |
| AD976BRSZ-RL7 | 功能描述:IC ADC 16BIT 100KSPS 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
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