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參數(shù)資料
| 型號： | AD976BRRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 100KSPS 28-SOIC |
| 標準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 100mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，雙極 |
| 配用： | EVAL-AD976CB-ND - BOARD EVAL FOR AD976 EVAL-AD976ACB-ND - BOARD EVAL FOR AD976A |
AD976/AD976A
–9–
REV. C
R/
C
CS
BYTE
PINS 6–13
PINS 15–22
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
HIGH BYTE
LOW BYTE
HI-Z
t
14
t
12
t
12
t
14
t
9
Figure 4. Using CS and BYTE to Control Data Bus Read Timing
Regardless of the method for controlling conversions, output
data from conversion “n–1” will be valid during the BUSY Low
time for roughly 3.7
s (AD976A only), and output data from
conversion “n” will be valid at the end of a conversion, 50 ns
(t10) before BUSY returns High. It is recommended, however,
that data is read only after BUSY goes high since this timing is
much more clearly defined and provides optimal performance.
Figure 4 demonstrates the functionality of the BYTE pin and
shows how the data will be valid in Binary Twos Complement
format only when R/C is asserted High and CS is Low. The
BYTE pin enables the output data on the bus to be read as a
full parallel output or as two 8-bit bytes on Pins 6–13 and Pins
15–22.
ANALOG INPUTS
Figure 5 shows the analog input section for the AD976 when
operating with an internal reference. The analog input range is
nominally a bipolar –10 V to +10 V. Since the AD976/AD976A
can be operated with an internal or external reference, the full-
scale analog input range can be best represented as
±4 V
REF.
The nominal input impedance is 23 k
/13 k with a 22 pF
input capacitance. The analog input section also has a
±25 V
overvoltage protection. Since the AD976/AD976A has two
analog grounds it is important to ensure that the analog input is
referenced to the AGND1 pin, the low current ground. This
will minimize any problems associated with a resistive ground
drop. It is also important to ensure that the analog input of the
AD976/AD976A is driven by a low impedance source. With its
primarily resistive analog input circuitry, the ADC can be driven
by a wide selection of general purpose amplifiers.
To best match the low distortion requirements of the AD976/
AD976A, care should be taken in the selection of the drive
circuitry op amp. Figure 6 shows the analog input section for
the AD976A when operating with an internal reference only.
Figure 9 shows the analog input section for both the AD976 and
the AD976A when operating with an external reference.
VIN
AGND1
REF
CAP
AGND2
10V INPUT
R2
33.2k
C2
2.2 F
AD976
R1
200
C1
2.2 F
Figure 5.
±10 V Input Connection for the AD976 (Internal
Reference)
C1
2.2 F
R2
66.4k
VANA
VIN
AGND1
REF
CAP
AGND2
10V INPUT
C2
2.2 F
AD976A
R1
200
+5V
Figure 6.
±10 V Input Connection for the AD976A (Internal
Reference) Only
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