參數(shù)資料
型號(hào)： AD9776BSVZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/56頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT DUAL 1GSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 300mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 1G
AD9776/AD9778/AD9779
Rev. A | Page 41 of 56
POWER-DOWN AND SLEEP MODES
INTERLEAVED DATA MODE
The AD977x has a variety of power-down modes, so that the
digital engine, main TxDACs, or auxiliary DACs can be powered
down individually or together. Via the SPI port, the main TxDACs
can be placed in sleep or power-down mode. In sleep mode, the
TxDAC output is turned off, thus reducing power dissipation.
The reference remains powered on, however, so that recovery
from sleep mode is very fast. With the power-down mode bit
set (Register 0x00, Bit 4), all analog and digital circuitry, including
the reference, is powered down. The SPI port remains active in
this mode. This mode offers more substantial power savings
than sleep mode, but the turn-on time is much longer. The
auxiliary DACs also have the capability to be programmed into
sleep mode via the SPI port. The auto power-down enable bit
(Register 0x00, Bit 3) controls the power-down function for the
digital section of the devices. The auto power-down function
works in conjunction with the TXENABLE pin (Pin 39) according
to the following:
The TxEnable bit is dual function. In dual port mode, it is
simply used to power down the digital section of the devices. In
interleaved mode, the IQ data stream is synchronized to
TXENABLE. Therefore, to achieve IQ synchronization,
TXENABLE should be held low until an I data word is present at
the inputs to Data Port 1. If a DATACLK rising edge occurs
while TXENABLE is at a high logic level, IQ data becomes
synchronized to the DATACLK output. TXENABLE can remain
high and the input IQ data remains synchronized. To be
backwards-compatible with previous DACs from Analog
Devices, Inc. such as the AD9777 and AD9786, the user can
also toggle TXENABLE once during each data input cycle, thus
continually updating the synchronization. If TXENABLE is
brought low and held low for multiple REFCLK cycles, then the
devices flush the data in the interpolation filters, and shut down
the digital engine after the filters are flushed. The amount of
REFCLK cycles it takes to go into this power-down mode is
then a function of the length of the equivalent 2×, 4×, or 8×
interpolation filter. The timing of TXENABLE, I/Q select, filter
flush, and digital power-down are shown in Figure 91.
TXENABLE (Pin 39) =
0: autopower-down enable =
0: flush data path with 0s
1: flush data for multiple REFCLK cycles; then
automatically place the digital engine in power-down
state. DACs, reference, and SPI port are not affected.
INTERLEAVED
INPUT DATA
TxENABLE CAN REMAIN
HIGH OR TOGGLE FOR
I/Q SYNCHRONIZATION
I1
Q1
I2
Q2
TxENABLE
FLUSHING
INTERPOLATION
FILTERS
POWER
DOWN DIGITAL
SECTION
05361-
085
or TXENABLE (Pin 39) =
1: normal operation
As shown in Figure 90, the power dissipation saved by using the
power down mode is nearly proportional to the duty cycle of
the signal at the TXENABLE pin.
Figure 91. TXENABLE Function
The TXENABLE function can be inverted by changing the
status of Register 0x02, Bit 1. The other bit that controls IQ
ordering is the Q-first bit (Register 0x02, Bit 0). With the Q-first
bit reset to the default of 0, the IQ pairing that is latched is the
I1Q1, I2Q2, and so on. With IQ first set to 1, the first I data is
discarded and the pairing is I2Q1, I3Q2, and so on. Note that
with IQ-first set, the I data is still routed to the internal I
channel, the Q data is routed to the internal Q channel, and
only the pairing changes.
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
100
80
60
40
20
DUTY CYCLE (%)
POW
ER
SA
VIN
G
S
05361-119
2× INT
fDATA = 50MSPS
8× INT
fDATA = 50MSPS
2× INT
fDATA = 200MSPS
4× INT
fDATA = 50MSPS
4× INT
fDATA = 200MSPS
8× INT
fDATA = 200MSPS
TIMING INFORMATION
Figure 92 to Figure 95 show some of the various timing
possibilities when the PLL is enabled. The combination of the
settings of N2 and N3 from Figure 74 means that the reference
clock frequency can be a multiple of the actual input data rate.
Figure 92 to Figure 95 show, respectively, what the timing looks
like when N2/N3 = 1 and 2.
Figure 90. Power Savings Based on Duty Cycle of TxEnable
If the TxEnable invert bit (Register 0x02, Bit 1) is set, the
function of this TXENABLE pin is inverted.
In interleaved mode, set-up and hold times of DATACLK out to
data in are the same as those shown in Figure 92 to Figure 95. It
is recommended that any toggling of TXENABLE occur
concurrently with the digital data input updating. In this way,
timing margins between DATACLK, TXENABLE, and digital
input data are optimized.
相關(guān)PDF資料
PDF描述
ADDAC80D-CBI-V IC DAC 12BIT LOW COST 24-CDIP
AD7247KNZ IC DAC 12BIT W/AMP W/BUFF 24-DIP
VI-2NW-IV-F1 CONVERTER MOD DC/DC 5.5V 150W
AD7237KN IC DAC 12BIT LC2MOS DUAL 24-DIP
AD5363BCPZ IC DAC 14BIT 8CH SERIAL 56-LFCSP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9776BSVZRL 功能描述:IC DAC 12BIT DUAL 1GSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
AD9776-EB 制造商:Analog Devices 功能描述:AD9776 EVAL BOARD - Bulk
AD9776-EBZ 制造商:Analog Devices 功能描述:DUAL 12B, 1.0 GSPS TXDAC - Bulk
AD9777 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator
AD9777BSV 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 16-bit 80-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:16BIT 160 MSPS DUAL TXDAC+ D/A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Interface Ty
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*