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參數(shù)資料
| 型號： | AD9776BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 39/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT DUAL 1GSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 300mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 1G |
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AD9776/AD9778/AD9779
Rev. A | Page 44 of 56
Using Data Delay to Meet Timing Requirements
To meet strict timing requirements at input data rates of up to
250 MSPS, the AD977x has a fine timing feature. Fine timing
adjustments are made by programming values into the data
clock delay register (Register 0x04, Bits<7:4>). This register can
be used to add delay between the REFCLK in and the
DATACLK out. Figure 97 shows the default delay present when
DATACLK delay is disabled. The disable function bit is found
in Register 0x02, Bit 4. Figure 98 shows the delay present when
DATACLK delay is enabled and set to 0000. Figure 99 indicates
the delay when DATACLK delay is enabled and set to 1111.
Note that the setup and hold times specified for data to
DATACLK are defined for DATACLK delay disabled.
CH1 1.00V
Ω
TEK RUN: 5.00GS/s
SAMPLE
CH2 500mV
Ω
M2.00ns
CH1
420mV
Δ: 4.48nS
@: 40.28nS
2
1
05361-089
Figure 97. Delay from REFCLK to DATACLK with DATACLK Delay Disabled
CH1 1.00V
Ω
TEK RUN: 5.00GS/s
SAMPLE
CH2 500mV
Ω
M2.00ns
CH1
420mV
Δ: 4.76nS
@: 35.52nS
2
1
05361-090
Figure 98. Delay from REFCLK to DATACLK Out with DATACLK Delay = 0000
CH1 1.00V
Ω
TEK RUN: 5.00GS/s
SAMPLE
CH2 500mV
Ω
M2.00ns
CH1
420mV
Δ: 7.84nS
@: 32.44nS
2
1
05361-091
Figure 99. Delay from REFCLK to DATACLK Out with DATACLK Delay = 1111
The difference between the minimum delay shown in Figure 98
and the maximum delay shown in Figure 99 is the range
programmable using the DATACLK delay register. The delay
(in absolute time) when programming DATACLK delay
between 0000 and 1111 is a linear extrapolation between these
two figures. The typical delays per increment over temperature
are shown in Table 20.
Table 20. Data Delay Line Typical Delays Over Temperature
Delays
40°C
+25°C
+85°C
Unit
Delay Between Disabled and
Enabled
370
416
432
ps
Average Delay per Increment
171
183
197
ps
The frequency of DATACLK out depends on several program-
mable settings: interpolation, zero stuffing, and interleaved/
dual port mode, all of which have an effect on the REFCLK
frequency. The divisor function between REFCLK and
DATACLK is equal to the values shown in Table 21.
Table 21. REFCLK to DATACLK Divisor Ratio
Interpolation
Zero Stuffing
Input Mode
Divisor
1
Disabled
Dual port
1
2
Disabled
Dual port
2
4
Disabled
Dual port
4
8
Disabled
Dual port
8
1
Disabled
Interleaved
Invalid
2
Disabled
Interleaved
1
4
Disabled
Interleaved
2
8
Disabled
Interleaved
4
1
Enabled
Dual port
2
Enabled
Dual port
4
Enabled
Dual port
8
Enabled
Dual port
16
1
Enabled
Interleaved
1
2
Enabled
Interleaved
2
4
Enabled
Interleaved
4
8
Enabled
Interleaved
8
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| AD9776BSVZRL | 功能描述:IC DAC 12BIT DUAL 1GSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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