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參數(shù)資料
| 型號(hào)： | AD9785BSVZRL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 22/64頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT 800MSPS 100TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | TxDAC® |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 29 of 64
The PLL control (PLLCTL) register comprises three bytes located at Address 0x04. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 14. PLL Control (PLLCTL) Register
Address
Bit
Name
Description
0x04
[23:21]
VCO Control Voltage
[2:0]
000 to 111, proportional to voltage at VCO, control voltage input (readback only). A value of
011 indicates that the VCO control voltage is centered.
[20:16]
PLL Loop Bandwidth
[4:0]
These bits control the bandwidth of the PLL filter. Increasing the value lowers the loop
bandwidth. Set to 01111 for optimal performance.
[15]
PLL enable
0: Default. With PLL off, the DAC sample clock is sourced directly by the REFCLK input.
1: With PLL on, the DAC clock is synthesized internally from the REFCLK input via the PLL
clock multiplier. See the Clock Multiplication section for details.
[14:13]
PLL VCO Divisor [1:0]
Sets the value of the VCO output divider, which determines the ratio of the VCO output
frequency to the DAC sample clock frequency, fVCO/fDACCLK.
00: fVCO/fDACCLK = 1
01: fVCO/fDACCLK = 2
10: fVCO/fDACCLK = 4
11: fVCO/fDACCLK = 8
[12:11]
PLL Loop Divisor [1:0]
Sets the value of the DACCLK divider, which determines the ratio of the DAC sample clock
frequency to the REFCLK frequency, fDACCLK/fREFCLK.
00: fDACCLK/fREFCLK = 2
01: fDACCLK/fREFCLK = 4
10: fDACCLK/fREFCLK = 8
11: fDACCLK/fREFCLK = 16
[10:8]
PLL Bias [2:0]
These bits control the VCO bias current. Set to 011 for optimal performance.
[7:2]
PLL Band Select [5:0]
These bits set the operating frequency of the VCO. For further details, refer to Table 35.
[1:0]
PLL VCO Drive [1:0]
These bits control the signal strength of the VCO output. Set to 11 for optimal performance.
The I DAC control register comprises two bytes located at Address 0x05. These bits are routed directly to the periphery of the digital
logic. No digital functionality within the main digital block is required.
Table 15. I DAC Control Register
Address
Bit
Name
Description
0x05
[15]
I DAC sleep
0: Default. If the I DAC sleep bit is cleared, the I DAC is active.
1: If the I DAC sleep bit is set, the I DAC is inactive and enters a low power state.
[14]
I DAC power-down
0: Default. If the I DAC power-down bit is cleared, the I DAC is active.
1: If the I DAC power-down bit is set, the I DAC is inactive and enters a low power state.
[13:10]
Reserved
Reserved for future use.
[9:0]
I DAC gain
adjustment
These bits are the I DAC gain adjustment bits.
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