- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17062 > AD9786-EBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9786 PDF資料下載
參數(shù)資料
| 型號： | AD9786-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9786 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD9786 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
AD9786
Rev. B | Page 27 of 56
CLOCK/DATA TIMING
Table 26. Data Port Synchronization
DCLKEXT
0x02, Bit 3
MODSYNC
0x05, Bit 3
DCLKCRC
0x02, Bit 2
Mode
Function
1
0
X
DATACLK Master
Channel data rate clock output
1
X
Modulator Master
Modulator synchronization
DATACLK output
0
External Sync Mode
DATACLK inactive, DACCLK
synchronous with external data
0
1
DATACLK Slave
DATACLK input, data rate clock,
data recovery on
0
1
0
Low Setup/Hold
DATACLK input, input data
synchronous with DATACLK
0
1
Modulator Slave
Input modulator synchronizer
DATACLK input
Two-Port Data Input Mode (DATACLK Master)
With the interpolation set to 1×, the DATACLK output is a
delayed and inverted version of DACCLK at the same frequency.
Note that DACCLK refers to the differential clock inputs applied
at Pin 5 and Pin 6. As Figure 44 and Figure 45 show, there is a
constant delay between the edges of DACCLK and DATACLK.
The DCLKPOL bit (Register 0x02, Bit 4) allows the data to be
latched into the AD9786 upon either the rising or falling edge
of DACCLK. With DCLKPOL = 0, the data is latched in upon
the falling edge of DACCLK, as shown in Figure 44. With
DCLKPOL = 1, as shown in Figure 45, data is latched in upon
the rising edge of DACCLK. The setup and hold times are
always with respect to the latching edge of DACCLK.
03152-044
DACCLKIN
DATACLKOUT
DATA
t12
tD = 6ns TYP
tH = 2.9ns MIN
tS = –0.5ns MIN
Figure 44. Data Timing, 1× Interpolation, DCLKPOL = 0
03152-045
DACCLKIN
DATACLKOUT
DATA
tD = 5.5ns TYP
tH = 2.9ns MIN
tS = –0.5ns MIN
Figure 45. Data Timing, 1× Interpolation, DCLKPOL = 1
With the interpolation set to 2×, the DACCLK input runs at
twice the speed of the DATACLK. Data is latched into the digital
inputs of the AD9786 upon every other rising edge of DACCLK,
as shown in Figure 47 and Figure 48. With DCLKPOL = 0, as
shown in Figure 47, the latching edge of DACCLK is the rising
edge that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, as in Figure 48, the latching edge of DACCLK is
the rising edge of DACCLK that occurs just before the rising edge
of DATACLK. The setup and hold time values are identical to
those in Figure 44 and Figure 45.
Note that there is a slight difference in the delay from the rising
edge of DACCLK to the falling edge of DATACLK, and the
delay from the rising edge of DACCLK to the rising edge of
DATACLK. As Figure 46 shows, the DATACLK duty cycle is
slightly less than 50%. This is true in all modes.
With the interpolation set to 4× or 8×, the DACCLK input
runs at 4× or 8× the speed of the DATACLK output. The data
is latched in upon a rising edge of DACCLK, similar to the
2× interpolation mode.
However, the latching edge is every fourth edge in 4× inter-
polation mode and every eighth edge in the 8× interpolation
mode. Similar to operation in the 2× interpolation mode, with
DCLKPOL = 0, the latching edge of DACCLK is the rising edge
that occurs just before the falling edge of DATACLK. With
DCLKPOL = 1, the latching edge of DACCLK is the rising
edge that occurs just before the rising edge of DATACLK.
The setup and hold time values are identical to those in 1×
and 2× interpolation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MIC2099-1YMT TR | IC DISTRIBUTION SWITCH |
| RCA10DRMI-S288 | CONN EDGECARD 20POS .125 EXTEND |
| HBM11DSEN-S243 | CONN EDGECARD 22POS .156 EYELET |
| AD9772A-EBZ | BOARD EVAL FOR AD9772A |
| ECE-V1VA101UP | CAP ALUM 100UF 35V 20% SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9786XSV | 制造商:Analog Devices 功能描述:- Bulk |
| AD9787 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual 12-/14-/16-Bit 800 MSPS DAC with Low Power 32-Bit Complex NCO |
| AD9787BSVZ | 功能描述:IC DAC 14BIT 800MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9787BSVZRL | 功能描述:IC DAC 14BIT 800MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9787-DPG2-EBZ | 功能描述:BOARD EVALUATION FOR AD9787 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。