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| 型號： | AD9786-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 39/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9786 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD9786 |
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AD9786
Rev. B | Page 44 of 56
OPERATING THE AD9786 REV. F EVALUATION BOARD
This section provides information to power up the board and
verify correct operation; a description of more advanced modes
of operation has been omitted.
POWER SUPPLIES
The AD9786 Rev. F evaluation board has five power supply
connectors, labeled AVDD1, AVDD2, ACVDD/ADVDD,
CLKVDD, and DVDD, whereas the AD9786 has seven power
supply domains. To reconcile the power supply domains on the
chip with the power supply connectors on the evaluation board,
use Table 38.
Additionally, the DRVDD power supply on the AD9786 is used
to supply power for the digital input bus. DRVDD should be
run from 3.3 V. On the evaluation board, DRVDD is jumper-
selectable by JP1, which is just to the left of the chip on the
evaluation board. With the jumper set to the 3.3 V position, the
DRVDD chip receives its power from VDD3IN.
PECL CLOCK DRIVER
The AD9786 system clock is driven from an external source via
Connector S1. The AD9786 evaluation board includes an
ON Semiconductor MC100EPT22 PECL clock driver. In the
factory, the evaluation board is set to use this PECL driver as a
single-ended-to-differential clock receiver. The PECL driver can
be set to run from 2.5 V from the CLKVDD power connector
or 3.3 V from the VDD3IN power connector. This setting is
done via Jumper JP2, situated next to the CLKVDD power
connector, and by setting Input Bias Resistor R23 and Input
Bias Resistor R4 on the evaluation board. The factory default is
for the PECL driver to be powered from CLKVDD at 2.5 V
(R23 = 90.9 Ω, R4 = 115 Ω). To operate the PECL driver with
a 3.3 V supply, R23 must be replaced with a 115 Ω resistor; R4
must be replaced with a 90.9 Ω resistor; and the position of JP2
must be changed. The schematic of the PECL driver section of
the evaluation board is shown in Figure 85. A low jitter sine
wave should be used as the clock source. Care must be taken to
ensure that the clock amplitude does not exceed the power
supply rails for the PECL driver.
03152-085
U2
7
1
2
COND;5
CLKVDDS;8
C32
0.1
μF
R23
115
Ω
R4
90.9
Ω
ACLKX
CLKVDDS
R5
50
Ω
R7
50
Ω
R6
50
Ω
CLKVDDS
MC100EPT22
CLK+
CLK–
Figure 85. PECL Driver on AD9786 Rev. F Evaluation Board
Table 38. Power Supply Domains on AD9786 Rev. F Evaluation Board
Evaluation Board Label/PS Domain on Chip
Nominal Power
Supply Voltage (V)
Description
DVDD
2.5
SPI port
CLKVDD
2.5
Clock circuitry
ACVDD/ADVDD
2.5
Analog circuitry containing clock and digital interface circuitry
AVDD2
3.3
Switching analog circuitry
AVDD1
3.3
Analog output circuitry
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