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參數(shù)資料
| 型號： | AD9786-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9786 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC+® |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 500M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD9786 |
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AD9786
Rev. B | Page 28 of 56
03152-046
Figure 46. DATACLK Duty Cycle
03152-047
tD = 6ns TYP
tH = 2.9ns MIN
tS = –0.5ns MIN
DACCLKIN
DATACLKOUT
DATA
Figure 47. Data Timing, 2× Interpolation, DCLKPOL = 0
tD = 5ns TYP
tS = –0.5ns MIN
tH = 2.9ns MIN
DACCLKIN
DATACLKOUT
DATA
03152-048
Figure 48. Data Timing, 2× Interpolation, DCLKPOL = 1
DATACLK Slave Mode (Data Recovery On)
DATACLK (Pin 31) can be used as an input to synchronize
multiple AD9786s. A clock generated by an AD9786 operating
in master mode, or a clock from an external source, can be used
to drive DATACLK.
In this mode, two clocks are required to be applied to the
AD9786. A clock running at the DAC sample rate, referred to as
DACCLK, must be applied to the differential inputs (Pin 5 and
Pin 6) of the AD9786. As described previously, a clock at the
input sample rate must also be applied to Pin 31 (DATACLK).
An internal DLL synchronizes the two applied clocks. The
timing relationships between the input data, DATACLK, and
DACCLK are given in Figure 49 and Figure 50.
Note that DCLKPOL (Register 0x02, Bit 4) can be used to select
the edge of DACCLK upon which the input data is latched.
There is a defined setup-and-hold window with respect to input
data and the latching edge of DACCLK. There is also a required
timing relationship between DATACLK and DACCLK. This is
referred to in Figure 49 and Figure 50 as tST and tHT (setup and
hold for transition). For example, with DCLKPOL set to Logic 0,
the input data latches upon the first rising edge of DACCLK
that occurs more than 1.5 ns before the falling edge of DATACLK.
DACCLK should not be given a rising edge in the window of
500 ps to 1.5 ns before the latching edge (falling edge when
DCLKPOL = 0, rising edge when DCLKPOL = 1) of DATACLK.
Failure to account for this timing relationship could result in
corrupt data.
There are three status bits available for a read that allow the user
to verify DLL lock. These are Bit 0, Bit 1, and Bit 2 (DCRCSTAT) in
Register 0x12.
03152-049
DACCLKIN
DATACLKIN
DATA
tHT = 1.5ns MIN
tS = 0.0ns MIN
tST = –500ps MIN
tH = 3.2ns MIN
Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0
03152-050
DACCLKIN
DATACLKIN
DATA
tHT = 2.0ns MIN
tS = 0.0ns MIN
tST = –1.0ns MIN
tH = 3.2ns MIN
Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1
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