參數(shù)資料
型號： AD9788-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 42/64頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9788
設(shè)計資源： Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
標準包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 800M
數(shù)據(jù)接口： 串行
設(shè)置時間： 22ms
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9788
AD9785/AD9787/AD9788
Rev. A | Page 47 of 64
DRIVING THE REFCLK INPUT
The REFCLK input requires a low jitter differential drive signal.
REFCLK is a PMOS input differential pair powered from the 1.8 V
supply; therefore, it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. Although these input levels are not directly LVDS-
compatible, REFCLK can be driven by an offset ac-coupled
LVDS signal, as shown in Figure 65.
LVDS_P_IN
REFCLK+
50
0.1F
LVDS_N_IN
REFCLK–
VCM = 400mV
07
09
8-
02
4
Figure 65. LVDS REFCLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to REFCLK, as shown in Figure 66. Use of a CMOS or TTL
clock is also acceptable for lower sample rates. It can be routed
through a CMOS-to-LVDS translator, then ac-coupled.
50
TTL OR CMOS
CLK INPUT
REFCLK+
REFCLK–
VCM = 400mV
BAV99ZXCT
HIGH SPEED
DUAL DIODE
0.1F
07
09
8-
0
25
Figure 66. TTL or CMOS REFCLK Drive Circuit
A simple bias network for generating VCM is shown in Figure 67.
It is important to use CVDD18 and CGND for the clock bias
circuit. Any noise or other signal that is coupled onto the clock
is multiplied by the DAC digital input signal and can degrade
DAC performance.
0.1
F1nF
1nF
VCM = 400mV
CVDD18
CGND
1k
287
07
09
8-
0
26
Figure 67. REFCLK VCM Generator Circuit
DAC REFCLK CONFIGURATION
The AD9785/AD9787/AD9788 offer two modes of sourcing
the DAC sample clock (DACCLK). The first mode employs an
on-chip clock multiplier that accepts a reference clock operating
at the lower input frequency, most commonly the data input
frequency. The on-chip phase-locked loop (PLL) then multiplies
the reference clock up to a higher frequency, which can then be
used to generate all the internal clocks required by the DAC.
The clock multiplier provides a high quality clock that meets
the performance requirements of most applications. Using the
on-chip clock multiplier removes the burden of generating and
distributing the high speed DACCLK.
The second mode bypasses the clock multiplier circuitry and
allows DACCLK to be directly sourced through the REFCLK
pins. This mode enables the user to source a very high quality
clock directly to the DAC core. Sourcing the DACCLK directly
through the REFCLK pins may be necessary in demanding
applications that require the lowest possible DAC output noise
at higher output frequencies.
In either case, using the on-chip clock multiplier or sourcing
the DACCLK directly through the REFCLK pins, it is necessary
that the REFCLK signal have low jitter to maximize the DAC
noise performance.
Direct Clocking
When the PLL is disabled (Register 0x04, Bit 15 = 0), the
REFCLK input is used directly as the DAC sample clock
(DACCLK). The output frequency of the DATACLK output
pin is
fDATACLK = fDACCLK/(IF × P)
where IF is the interpolation factor, set in Register 0x01, Bits [7:6],
and P = 0.5 if in single-port mode.
Clock Multiplication
When the PLL is enabled (Register 0x04, Bit 15 = 1), the clock
multiplication circuit generates the DAC sample clock from the
lower rate REFCLK input. The functional diagram of the clock
multiplier is shown in Figure 68.
The clock multiplication circuit operates such that the VCO
outputs a frequency, fVCO, equal to the REFCLK input signal
frequency multiplied by N1 × N2.
fVCO = fREFCLK × (N1 × N2)
The DAC sample clock frequency, fDACCLK, is equal to
fDACCLK = fREFCLK × N2
The values of N1 and N2 must be chosen to keep fVCO in the
optimal operating range of 1.0 GHz to 2.0 GHz. When the VCO
output frequency is known, the correct PLL band select value
(Register 0x04, Bits [7:2]) can be chosen.
PLL Bias Settings
There are three bias settings for the PLL circuitry that should be
programmed to their nominal values. The PLL values shown in
Table 34 are the recommended settings for these parameters.
Table 34. PLL Settings
PLL SPI Control
Address
Optimal
Setting
Register
Bit
PLL Loop Bandwidth
0x04
[20:16]
01111
PLL VCO Drive
0x04
[1:0]
11
PLL Bias
0x04
[10:8]
011
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