參數(shù)資料
型號(hào): AD9880KSTZ-150
廠商: Analog Devices Inc
文件頁數(shù): 15/64頁
文件大?。?/td> 0K
描述: IC INTERFACE/HDMI 150MHZ 100LQFP
標(biāo)準(zhǔn)包裝: 1
應(yīng)用: 視頻
接口: 模擬,HDMI
電源電壓: 3.15 V ~ 3.47 V
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 托盤
安裝類型: 表面貼裝
產(chǎn)品目錄頁面: 775 (CN2011-ZH PDF)
配用: AD9880/PCBZ-ND - KIT EVALUATION AD9880
AD9880
Rev. 0 | Page 22 of 64
DATAIN
P0
P1
P2
P5
P3
P4
P9
P6
P8
P10
P11
P7
HSIN
DATACLK
8 CLOCK CYCLE DELAY
DATAOUT
P0
P1
P2
P3
2 CLOCK CYCLE DELAY
HSOUT
05087-015
Figure 15. RGB ADC Timing
DATAIN
P0
P1
P2
P5
P3
P4
P9
P6
P8
P10
P11
P7
HSIN
DATACLK
8 CLOCK CYCLE DELAY
CB/CROUT
B0
R0
B2
R2
YOUT
Y0
Y1
Y2
Y3
2 CLOCK CYCLE DELAY
1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT.
2. EVEN NUMBER OF PIXEL DELAY BETWEEN HSOUT AND DATAOUT.
HSOUT
05087-016
Figure 16. YCrCb ADC Timing
Table 10.
Port
Red
Green
Blue
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
4:4:4
Red/Cr [7:0]
Green/Y [7:0]
Blue/Cb [7:0]
4:2:2
CbCr [7:0]
Y [7:0]
DDR 4:2:2 CbCr Y,Y
DDR 1 G [3:0]
DDR B [7:4]
DDR B [3:0]
DDR 4:2:2 CbCr [11:0]
4:4:4 DDR
DDR R [7:0]
DDR G [7:4]
DDR 4:2:2 Y,Y [11:0]
4:2:2-12
CbCr [11:0]
Y [11:0]
1 Arrows in the table indicate clock edge. Rising edge of clock =
↑, falling edge = ↓.
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