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參數(shù)資料
| 型號： | AD9880KSTZ-150 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE/HDMI 150MHZ 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 視頻 |
| 接口： | 模擬，HDMI |
| 電源電壓： | 3.15 V ~ 3.47 V |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 775 (CN2011-ZH PDF) |
| 配用： | AD9880/PCBZ-ND - KIT EVALUATION AD9880 |
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AD9880
Rev. 0 | Page 11 of 64
Pin
Description
POWER SUPPLY1
VD (3.3 V)
Analog Power Supply.
These pins supply power to the ADCs and terminators. They should be as quiet and filtered as possible.
VDD (1.8 V – 3.3 V)
Digital Output Power Supply.
A large number of output pins (up to 27) switching at high speed (up to 150 MHz) generates many power supply
transients (noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize
output noise transferred into the sensitive analog circuitry. If the AD9880 is interfacing with lower voltage logic, VDD
may be connected to a lower supply voltage (as low as 1.8 V) for compatibility.
PVDD (1.8 V)
Clock Generator Power Supply.
The most sensitive portion of the AD9880 is the clock generation circuitry. These pins provide power to the clock PLL
and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins.
DVDD (1.8 V)
Digital Input Power Supply.
This supplies power to the digital logic.
GND
Ground.
The ground return for all circuitry on chip. It is recommended that the AD9880 be assembled on a single solid ground
plane, with careful attention to ground current paths.
1 The supplies should be sequenced such that VD and VDD are never less than 300 mV below DVDD. At no time should DVDD be more than 300 mV greater than VD or
VDD.
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