I2C Read and Write Operations Figure 40 shows th" />
參數(shù)資料
型號： ADAU1381BCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 29/84頁
文件大小： 0K
描述： IC AUDIO CODEC STEREO LN 32LFCSP
標準包裝： 5,000
類型： 立體聲音頻
數(shù)據(jù)接口： 串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無
S/N 比，標準 ADC / DAC (db)： 97 / 100
動態(tài)范圍，標準 ADC / DAC (db)： 96.5 / 100
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應商設備封裝： 32-LFCSP-VQ
包裝： 帶卷 (TR)
配用： EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 35 of 84
I2C Read and Write Operations
Figure 40 shows the timing of a single-word write operation.
Every ninth clock pulse, the ADAU1381 issues an acknowledge
by pulling SDA low.
Figure 41 shows the timing of a burst mode write sequence.
This figure shows an example where the target destination
registers are two bytes. The ADAU1381 knows to increment its
subaddress register every two bytes because the requested
subaddress corresponds to a register or memory area with a
2-byte word length.
The timing of a single-word read operation is shown in Figure 42.
Note that the first R/W bit is 0, indicating a write operation. This is
because the subaddress still needs to be written to set up the
internal address. After the ADAU1381 acknowledges the receipt
of the subaddress, the master must issue a repeated start command
followed by the chip address byte with the R/W bit set to 1 (read).
This causes the ADAU1381 SDA to reverse and begin driving
data back to the master. The master then responds every ninth
pulse with an acknowledge pulse to the ADAU1381.
Figure 43 shows the timing of a burst mode read sequence. This
figure shows an example where the target read registers are two
bytes. The ADAU1381 increments its subaddress every two bytes
because the requested subaddress corresponds to a register or
memory area with word lengths of two bytes. Other address
ranges may have a variety of word lengths ranging from one to
five bytes. The ADAU1381 always decodes the subaddress and
sets the auto-increment circuit so that the address increments
after the appropriate number of bytes.
S
AS
SUBADDRESS,
LOW BYTE
AS
...
AS
P
CHIP ADDRESS,
R/W = 0
DATA
BYTE 1
DATA
BYTE 2
DATA
BYTE N
SUBADDRESS,
HIGH BYTE
S = START BIT, P = STOP BIT, AS = ACKNOWLEDGE BY SLAVE.
SHOWS A ONE-WORD WRITE, WHERE EACH WORD HAS N BYTES.
08
313
-038
Figure 40. Single-Word I2C Write Sequence
S
AS
ASAS
AS
ASAS
AS
...
P
CHIP
ADDRESS,
R/W = 0
SUBADDRESS,
HIGH BYTE
SUBADDRESS,
LOW BYTE
DATA-WORD 1,
BYTE 1
DATA-WORD 1,
BYTE 2
DATA-WORD 2,
BYTE 1
DATA-WORD 2,
BYTE 2
DATA-WORD N,
BYTE 1
DATA-WORD N,
BYTE 2
S = START BIT, P = STOP BIT, AS = ACKNOWLEDGE BY SLAVE.
SHOWS AN N-WORD WRITE, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)
0
83
13
-0
39
Figure 41. Burst Mode I2C Write Sequence
S
AM
AS
AM
AS
S
AS
...
P
CHIP ADDRESS,
R/W = 0
CHIP ADDRESS,
R/W = 1
DATA
BYTE N
DATA
BYTE 2
DATA
BYTE 1
SUBADDRESS,
HIGH BYTE
SUBADDRESS,
LOW BYTE
S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.
SHOWS A ONE-WORD READ, WHERE EACH WORD HAS N BYTES.
08
31
3-
04
0
Figure 42. Single-Word I2C Read Sequence
S
SAS
AS
AM
...
P
CHIP
ADDRESS,
R/W = 0
SUBADDRESS,
HIGH BYTE
SUBADDRESS,
LOW BYTE
DATA-WORD 1,
BYTE 1
DATA-WORD 1,
BYTE 2
DATA-WORD N,
BYTE 1
DATA-WORD N,
BYTE 2
CHIP
ADDRESS,
R/W = 1
S = START BIT, P = STOP BIT, AM = ACKNOWLEDGE BY MASTER, AS = ACKNOWLEDGE BY SLAVE.
SHOWS AN N-WORD READ, WHERE EACH WORD HAS TWO BYTES. (OTHER WORD LENGTHS ARE POSSIBLE, RANGING FROM ONE TO FIVE BYTES.)
08
31
3-
0
41
Figure 43. Burst Mode I2C Read Sequence
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