參數(shù)資料
型號(hào)： ADC10158
廠商： National Semiconductor Corporation
英文描述： Low-Voltage High-Speed Quadruple Differential Line Receiver 16-SOIC 0 to 70
中文描述： 10位帶符號(hào)4レs的4模數(shù)轉(zhuǎn)換器-或8通道多路復(fù)用器，采樣/保持和參考
文件頁(yè)數(shù)： 2/23頁(yè)
文件大?。?/td> 439K
代理商： ADC10158
Connection Diagrams
Pin Descriptions
AV
+
This is the positive analog supply. This pin
should be bypassed with a 0.1 μF ceramic ca-
pacitor and a 10 μF tantalum capacitor to the
system analog ground.
DV
+
This is the positive digital supply. This supply
pin also needs to be bypassed with 0.1 μF ce-
ramic and 10 μF tantalum capacitors to the
system digital ground. AV
+
and DV
+
should be
bypassed separately and tied to same power
supply.
DGND
This is the digital ground.All logic levels are re-
ferred to this ground.
V
This is the negative analog supply. For unipolar
operation this pin may be tied to the system
analog ground or to a negative supply source.
It should not go above DGND by more than
50 mV. When bipolar operation is required, the
voltage on this pin will limit the analog input’s
negative voltage level. In bipolar operation this
supply pin needs to be bypassed with 0.1 μF
ceramic and 10 μF tantalum capacitors to the
system analog ground.
V
REF+
,
V
REF
inputs. The voltage difference between V
REF+
and V
REF
will set the analog input voltage
span.
V
REF
Out
This is the internal band-gap voltage reference
output. For proper operation of the voltage ref-
erence, this pin needs to be bypassed with a
330 μF tantalum or electrolytic capacitor.
CS
This is the chip select input. When a logic low
is applied to this pin the WR and RD pins are
enabled.
These are the positive and negative reference
RD
This is the read control input. When a logic low
is applied to this pin the digital outputs are en-
abled and the INT output is reset high.
This is the write control input. The rising edge
of the signal applied to this pin selects the mul-
tiplexer channel and initiates a conversion.
This is the interrupt output. A logic low at this
output indicates the completion of a conver-
sion.
This is the clock input. The clock frequency di-
rectly controls the duration of the conversion
time (for example, in the 10-bit bipolar mode
t
C
= 22/f
CLK
) and the acquisition time (t
A
=
6/f
CLK
).
These are the digital data inputs/outputs. DB0
is the least significant bit of the digital output
word; DB7 is the most significant bit in the digi-
tal output word (see the Output Data Configu-
ration table). MA0 through MA4 are the digital
inputs for the multiplexer channel selection
(see the Multiplexer Addressing tables). U/S
(Unsigned/Signed), 8/10, (8/10-bit resolution)
and L/R (Left/Right justification) are the digital
input bits that set the A/D’s output word format
and resolution (see the Output Data Configura-
tion table). The conversion time is modified by
the chosen resolution (see Electrical AC Char-
acteristics table). The lower the resolution, the
faster the conversion will be.
These are the analog input multiplexer chan-
nels. They can be configured as single-ended
inputs,
differential
pseudo-differential inputs (see the Multiplexer
Addressing
tables
for
assignments).
WR
INT
CLK
DB0(MA0)
–DB7 (L/R)
CH0–CH7
input
pairs,
or
the
input
polarity
Dual-in-Line and SO Packages
DS011225-2
Top View
Order Number ADC10154
NS Package Number M24B
Dual-in-Line and SO Packages
DS011225-3
Top View
Order Number ADC10158
NS Package Numbers
M28B or N28B
A
www.national.com
2
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