- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378281 > ADC10158CIWM (NATIONAL SEMICONDUCTOR CORP) 10-Bit Plus Sign 4 レs ADCs with 4- or 8-Channel MUX, Track/Hold and Reference PDF資料下載
參數(shù)資料
| 型號： | ADC10158CIWM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | ADC |
| 英文描述： | 10-Bit Plus Sign 4 レs ADCs with 4- or 8-Channel MUX, Track/Hold and Reference |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大小： | 439K |
| 代理商： | ADC10158CIWM |
2.0 Applications Information
(Continued)
code transition from 000 0000 0000 to 000 0000 0001
(10-bits plus sign) and the ideal
1
2
LSB value (
1
2
LSB=2.44
mV for V
REF
= + 5.000V and 10-bit plus sign resolution).
The zero error of the A/D does not require adjustment. If the
minimum analog input voltage value, V
(Min), is not ground,
the effetive “zero” voltage can be adjusted to a convenient
value. The converter can be made to output an all zeros digi-
tal code for this minimum input voltage by biasing any minus
input to V
(Min). This is useful for either the differential or
pseudo-differential input channel configurations.
2.4.2 Full-Scale
The full-scale adjustment can be made by applying a differ-
ential input voltage which is 1
1
2
LSB down from the desired
analog full-scale voltage range and then adjusting the V
voltage (V
= V
REF+
V
REF
) for a digital output code
changing from 011 1111 1110 to 011 1111 1111. In bipolar
signed operation this only adjusts the positive full scale error.
The negative full-scale error will be as specified in the Elec-
trical Characteristics after a positive full-scale adjustment.
2.4.3 Adjusting for an Arbitrary Analog Input
Voltage Range
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input signal
which does not go to ground), this new zero reference
should be properly adjusted first. A plus input voltage which
equals this desired zero reference plus
1
2
LSB (where the
LSB is calculated for the desired analog span, using 1 LSB=
analog span/2
, n being the programmed resolution) is ap-
plied to selected plus input and the zero reference voltage at
the corresponding minus input should then be adjusted to
just obtain the 000
HEX
to 001
HEX
code transition.
The full-scale adjustment should be made [with the proper
minus input voltage applied] by forcing a voltage to the plus
input which is given by:
where V
equals the high end of the ananlog input range,
V
equals the low end (the offset zero) of the analog range
and n equals the programmed resolution. Both V
and
V
are ground referred. The V
(V
= V
REF+
V
REF
)
voltage is then adjusted to provide a code change from
3FE
to 3FF
. Note, when using a pseudo-differential
or differential multiplexer mode where V
REF+
and V
are
placed within the V
+
and V
range, the individual values of
V
REF+
and V
REF
do not matter, only the difference sets the
analog input voltage span. This completes the adjustment
procedure.
2.5 INPUT SAMPLE-AND-HOLD
The ADC10154/8’s sample/hold capacitor is implemented in
the capacitor array. After the channel address is loaded, the
array is switched to sample the selected positive analog in-
put. The rising edge of WR loads the multiplexer addressing
information. The sampling period for the assigned positive
input is maintained for the duration of the acquisition time
(t
), i.e., approximately 6 to 8 clock cycles after the rising
edge of WR.
An acquisition window of 6 clock cycles is available to allow
the voltage on the capacitor array to settle to the positive
analog input voltage. Any change in the analog voltage on a
selected positive input before or after the acquisition window
will not effect the A/D conversion result.
In the simplest case, the array’s acquisition time is deter-
mined by the R
(9 k
) of the multiplexer switches, the
stray input capacitance C
(3.5 pF) and the total array (C
L
)
and stray (C
) capacitance (C
+ C
= 48 pF). For a large
source resistance the analog input can be modeled as an
RC network as shown in Figure 6 The values shown yield an
acquisition time of about 1.1 μs for 10-bit unipolar or 10-bit
plus sign bipolar accuracy with a zero-to-full-scale change in
the input voltage. External source resistance and capaci-
tance will lengthen the acquisition time and should be ac-
counted for. Slowing the clock will lengthen the acquisition
time, thereby allowing a larger external source resistance.
The curve “Signal to Noise Ratio vs. Output Frequency” (Fig-
ure 7) gives an indication of the usable bandwidth of the
ADC10154/ADC10158. The signal-to-noise ratio of an ideal
A/D is the ratio of the RMS value of the full scale input signal
amplitude to the value of the total error amplitude (including
noise) caused by the transfer function of the A/D. An ideal
10-bit plus sign A/D converter with a total unadjusted error of
0 LSB would have a signal-to-noise ratio of about 68 dB,
which can be derived from the equation:
S/N = 6.02(n) + 1.76
where S/N is in dB and n is the number of bits. Figure 3
shows the signal-to-noise ratio vs. input frequency of a typi-
cal ADC10154/ADC10158 with
1
2
LSB total unadjusted er-
ror. The dotted lines show signal-to-noise ratios for an ideal
(noiseless) 10-bit A/D with 0 LSB error and an A/D with a 1
LSB error.
The sample-and-hold error specifications are included in the
error and timing specifications of the A/D. The hold step and
DS011225-23
FIGURE 6. Analog Input Model
SNR vs Input Frequency
DS011225-24
FIGURE 7. ADC10154/ADC10158
Signal-to-Noise Ratio vs Input Frequency
A
www.national.com
20
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADC10154 | Low-Voltage High-Speed Quadruple Differential Line Receiver 16-SOIC 0 to 70 |
| ADC10158 | Low-Voltage High-Speed Quadruple Differential Line Receiver 16-SOIC 0 to 70 |
| ADC10158CIN | 10-Bit Plus Sign 4 レs ADCs with 4- or 8-Channel MUX, Track/Hold and Reference |
| ADC1021 | 10-BIT uP COMPATIBLKE A/D CONVERTERS |
| ADC1021CCJ | 10-BIT uP COMPATIBLKE A/D CONVERTERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADC10158CIWM/48 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| ADC10158CIWM/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC10158CIWMX | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC10158CIWMX/NOPB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC10158CMJ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Ended Data Acquisition System |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。